參數(shù)資料
型號(hào)： R2061K
英文描述： real-time clock ICs
中文描述： 實(shí)時(shí)時(shí)鐘IC
文件頁(yè)數(shù)： 20/48頁(yè)
文件大小： 322K
代理商： R2061K
R2061 Series
I
Interfacing with the CPU
G
DATA TRANSFER FORMATS
(1) Timing Between CE Pin Transition and Data Input / Output
The R2061 adopts a 3-wire serial interface by which they use the CE (Chip Enable), SCLK (Serial Clock), and SIO
(Serial Input/Output) pins to receive and send data to and from the CPU. The 3-wire serial interface provides two
types of input/output timings with which the SIO pin output and input are synchronized with the rising or falling
edges of the SCLK pin input, respectively, and vice versa. The R2061 is configured to select either one of two
different input/output timings depending on the level of the SCLK pin in the low to high transition of the CE pin.
Namely, when the SCLK pin is held low in the low to high transition of the CE pin, the models will select the timing
with which the SIO pin output is synchronized with the rising edge of the SCLK pin input, and the input is
synchronized with the falling edge of the SCLK pin input, as illustrated in the timing chart below.
12345
Rev.1.00 - 20 -
SCLK
SIO (for reading)
t
DS
SIO (for writing)
CE
t
CES
t
DH
t
RD
Conversely, when the SCLK pin is held high in the low to high transition of the CE pin, the models will select the
timing with which the SIO pin output is synchronized with the falling edge of the SCLK pin input, and the input is
synchronized with the rising edge of the SCLK pin input, as illustrated in the timing chart below.
SCLK
SIO (for reading)
t
DS
SIO (for writing)
CE
t
CES
t
DH
t
RD
(2) Data Transfer Formats
Data transfer is commenced in the low to high transition of the CE pin input and completed in its high to low
transition. Data transfer is conducted serially in multiple units of 1 byte (8 bits). The former 4 bits are used to
specify in the Address Pointer a head address with which data transfer is to be commenced from the host. The
latter 4 bits are used to select either reading data transfer or writing data transfer, and to set the Transfer Format
Register to specify an appropriate data transfer format. All data transfer formats are designed to transfer the most
significant bit (MSB) first.
A2
CE
SCLK
6
A1
A0
C3
C2
C1
C0
A3
7
5
8
2
3
1
2
3
1
4
D7
D6
D3
D2
D1
D0
Setting
the Address Pointer
Writing or Reading data transfer
Setting the Transfer
Format Register
SIO
Two types of data transfer formats are available for reading data transfer and writing data transfer each.
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