R2061 Series
12345
Rev.1.00 - 33 -
When the PON bit is set to 1 in the control register 2, the DEV, F6 to F0, WALE, DALE, /12
24, SCRATCH2, TEST,
CT2, CT1, CT0, VDSL, VDET, SCRATCH1, CTFG, WAFG, and DAFG bits are reset to 0 in the oscillation
adjustment register, the control register 1, and the control register 2. The PON bit is also set to 1 at power-on from
0 volts.
< Considerations in Using Oscillation Halt Sensing Circuit >
Be sure to prevent the oscillation halt sensing circuit from malfunctioning by preventing the following:
1) Instantaneous power-down on the VDD
2) Condensation on the crystal oscillator
3) On-board noise to the crystal oscillator
4) Applying to individual pins voltage exceeding their respective maximum ratings
In particular, note that the /XST bit may fail to be set to 0 in the presence of any applied supply voltage as illustrated
below in such events as backup battery installation. Further, give special considerations to prevent excessive
chattering in the oscillation halt sensing circuit.
VDD
