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R2061 Series
I
Power-on Reset, Oscillation Halt Sensing, and Supply Voltage Monitoring
G
PON, /XST, and VDET
The power-on reset circuit is configured to reset control register1, 2, and clock adjustment register when VDD
power up from 0v. The oscillation halt sensing circuit is configured to record a halt on oscillation by 32.768-kHz
clock pulses. The supply voltage monitoring circuit is configured to record a drop in supply voltage below a
threshold voltage of 2.1 or 1.35v.
Each function has a monitor bit. I.e. the PON bit is for the power-on reset circuit, and /XST bit is for the oscillation
halt sensing circuit, and VDET is for the supply voltage monitoring circuit. PON and VDET bits are activated to “H”.
However, /XST bit is activated to “L”. The PON and VDET accept only the writing of 0, but /XST accepts the writing
of 0 and 1. The PON bit is set to 1, when VDD power-up from 0V, but VDET is set to 0, and /XST is
indefinite.
The functions of these three monitor bits are shown in the table below.
PON
/XST
Function
Monitoring for the power-on
reset function
oscillation halt sensing
function
Address
D4 in Address Fh
D5 in Address Fh
Activated
High
Low
When VDD power
up from 0v
accept the writing
0 only
Both 0 and 1
The relationship between the PON, /XST, and VDET is shown in the table below.
PON
/XST
VDET
Conditions of supply voltage and
oscillation
0
0
0
Halt on oscillation, but no drop in VDD
supply voltage below threshold voltage
0
0
1
Halt on oscillation and drop in VDD
supply
voltage
below
voltage, but no drop to 0V
0
1
0
No drop in VDD supply voltage below
threshold voltage and no halt in
oscillation
0
1
1
Drop in VDD supply voltage below
threshold voltage and no halt on
oscillation
1
*
*
Drop in supply voltage to 0v
12345
Rev.1.00 - 32 -
VDET
a drop in supply voltage
below a threshold voltage
of 2.1 or 1.35v
D6 in Address Fh
High
0
Monitoring for the
1
indefinite
0 only
Condition of oscillator, and back-up
status
Halt
on
oscillation
condensation etc.
Halt on oscillation cause of drop in
back-up battery voltage
cause
of
threshold
Normal condition
No halt on oscillation, but drop in
back-up battery voltage
Power-up from 0v,
32768Hz Oscillation
Power-on reset flag
(PON)
Oscillation halt
sensing flag (/XST)
Threshold voltage (2.1V or 1.35V)
VDD
VDD supply voltage
monitor flag (VDET)
Internal initialization
period (1 to 2 sec.)
VDET
←
0
/XST
←
1
PON
←
0
VDET
←
0
/XST
←
1
PON
←
1
VDET
←
0
/XST
←
1
PON
←
0
Internal initialization
period (1 to 2 sec.)