參數(shù)資料
型號： RC28F256P33T85A
廠商： NUMONYX
元件分類： PROM
英文描述： 16M X 16 FLASH 3V PROM, 85 ns, PBGA64
封裝： BGA-64
文件頁數(shù)： 30/96頁
文件大小： 1378K
代理商： RC28F256P33T85A
Numonyx StrataFlash Embedded Memory (P33)
Datasheet
November 2007
36
Order Number: 314749-05
7.4
AC Write Specifications
Table 19: AC Write Specifications
Num
Symbol
Parameter
Min
Max
Unit
Notes
W1
tPHWL
RST# high recovery to WE# low
150
-
ns
1,2,3
W2
tELWL
CE# setup to WE# low
0
-
ns
1,2,3
W3
tWLWH
WE# write pulse width low
50
-
ns
1,2,4
W4
tDVWH
Data setup to WE# high
50
-
ns
1,2
W5
tAVWH
Address setup to WE# high
50
-
ns
W6
tWHEH
CE# hold from WE# high
0
-
ns
W7
tWHDX
Data hold from WE# high
0
-
ns
W8
tWHAX
Address hold from WE# high
0
-
ns
W9
tWHWL
WE# pulse width high
20
-
ns
1,2,5
W10
tVPWH
VPP setup to WE# high
200
-
ns
1,2,3,7
W11
tQVVL
VPP hold from Status read
0
-
ns
W12
tQVBL
WP# hold from Status read
0
-
ns
1,2,3,7
W13
tBHWH
WP# setup to WE# high
200
-
ns
W14
tWHGL
WE# high to OE# low
0
-
ns
1,2,9
W16
tWHQV
WE# high to read valid
tAVQV + 35
-
ns
1,2,3,6,10
Write to Asynchronous Read Specifications
W18
tWHAV
WE# high to Address valid
0
-
ns
1,2,3,6,8
Write to Synchronous Read Specifications
W19
tWHCH/L
WE# high to Clock valid
19
-
ns
1,2,3,6,10
W20
tWHVH
WE# high to ADV# high
19
-
ns
Write Specifications with Clock Active
W21
tVHWL
ADV# high to WE# low
-
20
ns
1,2,3,11
W22
tCHWL
Clock high to WE# low
-
20
ns
Notes:
1.
Write timing characteristics during erase suspend are the same as write-only operations.
2.
A write operation can be terminated with either CE# or WE#.
3.
Sampled, not 100% tested.
4.
Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
(whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH.
5.
Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low
(whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = tEHWL).
6.
tWHVH or tWHCH/L must be met when transitioning from a write cycle to a synchronous burst read.
7.
VPP and WP# should be at a valid level until erase or program success is determined.
8.
This specification is only applicable when transitioning from a write cycle to an asynchronous read. See spec W19 and
W20 for synchronous read.
9.
When doing a Read Status operation following any command that alters the Status Register, W14 is 20 ns.
10.
Add 10 ns if the write operations results in a RCR or block lock status change, for the subsequent read operation to
reflect this change.
11.
These specs are required only when the device is in a synchronous mode and clock is active during address setup
phase.
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