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參數(shù)資料
| 型號： | RC28F256P33T85A |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 16M X 16 FLASH 3V PROM, 85 ns, PBGA64 |
| 封裝： | BGA-64 |
| 文件頁數(shù)： | 38/96頁 |
| 文件大?。?/td> | 1378K |
| 代理商： | RC28F256P33T85A |
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November 2007
Datasheet
Order Number: 314749-05
43
Numonyx StrataFlash Embedded Memory (P33)
9.0
Bus Operations
CE# low and RST# high enable device read operations. The device internally decodes
upper address inputs to determine the accessed block. ADV# low opens the internal
address latches. OE# low activates the outputs and gates selected data onto the I/O
bus.
In asynchronous mode, the address is latched when ADV# goes high or continuously
flows through if ADV# is held low. In synchronous mode, the address is latched by the
first of either the rising ADV# edge or the next valid CLK edge with ADV# low (WE#
and RST# must be VIH; CE# must be VIL).
Bus cycles to/from the Numonyx StrataFlash Embedded Memory (P33) device
conform to standard microprocessor bus operations. Table 22 summarizes the bus
operations and the logic levels that must be applied to the device control signal inputs.
9.1
Read
To perform a read operation, RST# and WE# must be deasserted while CE# and OE#
are asserted. CE# is the device-select control. When asserted, it enables the flash
memory device. OE# is the data-output control. When asserted, the addressed flash
memory data is driven onto the I/O bus.
9.2
Write
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are
deasserted. During a write operation, address and data are latched on the rising edge
of WE# or CE#, whichever occurs first. Table 23, “Command Bus Cycles” on page 45
shows the bus cycle sequence for each of the supported device commands, while
Table 24, “Command Codes and Definitions” on page 46 describes each command. See
Section 7.0, “AC Characteristics” on page 29 for signal-timing details.
Note:
Write operations with invalid VCC and/or VPP voltages can produce spurious results and
should not be attempted.
9.3
Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-
impedance (High-Z) state, WAIT is also placed in High-Z.
Table 22: Bus Operations Summary
Bus Operation
RST#
CLK
ADV#
CE#
OE#
WE#
WAIT
DQ[15:0]
Notes
Read
Asynchronous
VIH
XL
L
H
Deasserted
Output
Synchronous
VIH
Running
L
H
Driven
Output
Write
VIH
X
L
H
L
High-Z
Input
1
Output Disable
VIH
X
L
H
High-Z
2
Standby
VIH
X
H
X
High-Z
2
Reset
VIL
X
High-Z
2,3
Notes:
1.
Refer to the
Table 23, “Command Bus Cycles” on page 45 for valid DQ[15:0] during a write
operation.
2.
X = Don’t Care (H or L).
3.
RST# must be at VSS ± 0.2 V to meet the maximum specified power-down current.
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