參數(shù)資料
型號: RC28F256P33T85A
廠商: NUMONYX
元件分類: PROM
英文描述: 16M X 16 FLASH 3V PROM, 85 ns, PBGA64
封裝: BGA-64
文件頁數(shù): 46/96頁
文件大小: 1378K
代理商: RC28F256P33T85A
Numonyx StrataFlash Embedded Memory (P33)
Datasheet
November 2007
50
Order Number: 314749-05
11.1.0.2
Read Mode
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode
operation for the device. When the RM bit is set, asynchronous page mode is selected
(default). When RM is cleared, synchronous burst mode is selected.
11.1.0.3
Latency Count
The Latency Count (LC) bits tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the
first valid data word is driven onto DQ[15:0]. The input clock frequency is used to
determine this value and Figure 27 shows the data output latency for the different
settings of LC. The maximum Latency Count for P33 would be Code 4 based on the Max
clock frequency specification of 52 Mhz, and there will be zero WAIT States when
bursting within the word line. Please also refer to Section 11.1.0.12, “End of Word Line
(EOWL) Considerations” on page 55 for more information on EOWL.
Refer to Table 27, “LC and Frequency Support” on page 51 for Latency Code Settings.
10
Wait Polarity (WP)
0 =WAIT signal is active low
1 =WAIT signal is active high (default)
9
Data Hold (DH)
0 =Data held for a 1-clock data cycle
1 =Data held for a 2-clock data cycle (default)
8
Wait Delay (WD)
0 =WAIT deasserted with valid data
1 =WAIT deasserted one data cycle before valid data (default)
7
Burst Sequence (BS)
0 =Reserved
1 =Linear (default)
6
Clock Edge (CE)
0 = Falling edge
1 = Rising edge (default)
5:4
Reserved (R)
Reserved bits should be cleared (0)
3
Burst Wrap (BW)
0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
2:0
Burst Length (BL[2:0])
001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
(Other bit settings are reserved)
Note:
Latency Code 2, Data Hold for a 2-clock data cycle (DH = 1) WAIT must be deasserted with valid data (WD = 0).
Latency Code 2, Data Hold for a 2-cock data cycle (DH=1) WAIT deasserted one data cycle before valid data (WD = 1)
combination is not supported.
Table 26, “Read Configuration Register Description” is shown using the QUAD+ package. For EASY BGA
and TSOP packages, the table reference should be adjusted using address bits A[16:1].
Table 26: Read Configuration Register Description (Sheet 2 of 2)
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