參數(shù)資料
型號(hào)： RC28F256P33T85A
廠商： NUMONYX
元件分類： PROM
英文描述： 16M X 16 FLASH 3V PROM, 85 ns, PBGA64
封裝： BGA-64
文件頁(yè)數(shù)： 49/96頁(yè)
文件大?。?/td> 1378K
代理商： RC28F256P33T85A
November 2007
Datasheet
Order Number: 314749-05
53
Numonyx StrataFlash Embedded Memory (P33)
11.1.0.6
Data Hold
For burst read operations, the Data Hold (DH) bit determines whether the data output
remains valid on DQ[15:0] for one or two clock cycles. This period of time is called the
“data cycle”. When DH is set, output data is held for two clocks (default). When DH is
cleared, output data is held for one clock (see Figure 29). The processor’s data setup
time and the flash memory’s clock-to-data output delay should be considered when
determining whether to hold output data for one or two clocks. A method for
determining the DH configuration is shown below:
To set the device at one clock data hold for subsequent reads, the following condition
must be satisfied:
tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)
tDATA = Data set up to Clock (defined by CPU)
For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming
tCHQV = 20 ns and tDATA = 4 ns. Applying these values to the formula above:
20 ns + 4 ns ≤ 25 ns
The equation is satisfied and data will be available at every clock period with data hold
setting at one clock. If tCHQV (ns) + tDATA (ns) > One CLK Period (ns), data hold setting of
2 clock periods must be used.
11.1.0.7
WAIT Delay
The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during
synchronous burst reads. WAIT can be asserted either during or one data cycle before
valid data is output on DQ[15:0]. When WD is set, WAIT is deasserted one data cycle
before valid data (default). When WD is cleared, WAIT is deasserted during valid data.
All Asynchronous Reads
Deasserted
1
All Writes
High-Z
1,2
Notes:
1.
Active: WAIT is asserted until data becomes valid, then deasserts.
2.
When OE# = VIH during writes, WAIT = High-Z.
Table 28: WAIT Functionality Table (Sheet 2 of 2)
Condition
WAIT
Notes
Figure 29: Data Hold Timing
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
CLK [C]
D[15:0] [Q]
2 CLK
Data Hold
1 CLK
Data Hold
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