參數(shù)資料
型號： RG82845MZ
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 13/157頁
文件大?。?/td> 1407K
代理商： RG82845MZ
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
11
R
Terminology
MCH-M - The Mobile Memory Controller Hub-M component that contains the processor interface,
DRAM controller, and AGP interface. It communicates with the I/O controller hub (ICH3-M) and other
IO controller hubs over proprietary interconnect called the hub interface.
ICH3-M - The Mobile I/O Controller Hub 3-M component that contains the primary PCI interface, LPC
interface, USB, ATA-100, AC’97, and other IO functions. It communicates with the Intel
845MP/845MZ Chipset MCH-M over a proprietary interconnect called hub interface.
Host - This term is used synonymously with processor.
Core - The internal base logic in the MCH-M.
System Bus - Processor-to-MCH-M interface. The Enhanced Mode of the Scalable Bus is the P6 Bus
plus enhancements, consisting of source synchronous transfers for address and data, and system bus
interrupt delivery. The Mobile Intel Pentium 4 Processor-M implements a subset of Enhanced Mode.
Hub interface - The proprietary hub interconnect that ties the MCH-M to the ICH3-M. In this document
hub interface cycles originating from or destined for the primary PCI interface on the ICH3-M is
generally referred to as hub interface cycles.
Accelerated Graphics Port (AGP) - Refers to the AGP interface that is in the MCH-M. It supports
AGP 2.0 compliant components only with 1.5V signaling level. PIPE# and SBA addressing cycles and
their associated data phases are generally referred to as AGP transactions. FRAME# cycles over the AGP
bus are generally referred to as AGP/PCI transactions.
PCI_A - The physical PCI bus, driven directly by the ICH3-M component. It supports 5-V, 32-bit, 33-
MHz PCI 2.2 compliant components. Communication between PCI_A and MCH-M occurs over hub
interface. Note: Even though it is referred to as PCI_A it is not PCI Bus #0 from a configuration
standpoint.
Full Reset - A Full MCH-M Reset is defined in this document when RSTIN# is asserted.
System Bus - Synonymous with Host or Front Side Bus
GART - Graphics Aperture Re-map Table. This table contains the page re-map information used during
AGP aperture address translations.
GTLB - Graphics Translation Look-aside Buffer. A cache used to store frequently used GART entries.
UP – Uniprocessor
DBI – Dynamic Bus inversion
MSI – Message Signaled Interrupts. MSI’s allow a device to request interrupt service via a standard
Memory Write transaction instead of through a hardware signal.
IPI – Inter Processor Interrupt
Word – 16 bits = 2 bytes
Dword (DW) – Doubleword: 32bits = 4 bytes
相關PDF資料
PDF描述
RG82870P2 Controller Miscellaneous - Datasheet Reference
RH5RE36AA-T1-FA 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3
RH5RE56AA-T1-FA 5.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3
RE5RE36AA-TZ-FC 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PBCY3
RE5RE36AC-TZ-FC 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PBCY3
相關代理商/技術參數(shù)
參數(shù)描述
RG82845PE S L6H5 制造商:Intel 功能描述:CHIPSTGMCH 82845PE HT-PBGA760
RG82845PESL6Q3 制造商:Intel 功能描述:Chipsets
RG82845-SL5V7 制造商:Intel 功能描述:INTEL 845G GRAPHICS AND MEMORY CONTROLLER HUB(GMCH)
RG82845SL5YQ 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel?? 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR
RG82845-SL63W 制造商:Intel 功能描述:INTEL 845G GRAPHICS AND MEMORY CONTROLLER HUB(GMCH)
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*