參數(shù)資料
型號: RG82845MZ
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 142/157頁
文件大?。?/td> 1407K
代理商: RG82845MZ
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
85
R
3.8.
AGP Bridge Registers – Device #1
Table 24 shows the access attributes for configuration space.
Table 24. Nomenclature for Access Attributes
RO
Read Only. If a register is read only, writes to this register have no effect.
R/W
Read/Write. A register with this attribute can be read and written.
R/WC
Read/Write Clear. A register bit with this attribute can be read and written. However, a write of a 1
clears (sets to 0) the corresponding bit and a write of a 0 has no effect.
Table 25 summarizes the MCH-M configuration space for Device #1.
Table 25. MCH-M Configuration Space - Device #1
Address Offset
Register Symbol
Register Name
Default Value
Access
00-01h
VID1
Vendor Identification
8086h
RO
02-03h
DID1
Device Identification
1A31hh
RO
04-05h
PCICMD1
PCI Command Register
0000h
RO, R/W
06-07h
PCISTS1
PCI Status Register
00A0h
RO, R/WC
08
RID1
Revision Identification
Silicon Revision
RO
09
Reserved
0Ah
SUBC1
Sub-Class Code
04h
RO
0Bh
BCC1
Base Class Code
06h
RO
0Ch
Reserved
0Dh
MLT1
Master Latency Timer
00h
RO, R/W
0Eh
HDR1
Header Type
01h
RO
0F-17h
Reserved
18h
PBUSN1
Primary Bus Number
00h
RO
19h
SBUSN1
Secondary Bus Number
00h
R/W
1Ah
SUBUSN1
Subordinate Bus Number
00h
R/W
1Bh
SMLT1
Secondary Bus Master Latency
Timer
00h
RO, R/W
1Ch
IOBASE1
I/O Base Address Register
F0h
RO, R/W
1Dh
IOLIMIT1
I/O Limit Address Register
00h
RO, R/W
1E-1Fh
SSTS1
Secondary Status Register
02A0h
RO, R/WC
20-21h
MBASE1
Memory Base Address Register
FFF0h
RO, R/W
22-23h
MLIMIT1
Memory Limit Address Register
0000h
RO, R/W
24-25h
PMBASE1
Prefetchable Memory Base
Address Reg.
FFF0h
RO, R/W
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