- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄225036 > RG82845MZ Controller Miscellaneous - Datasheet Reference PDF資料下載
參數(shù)資料
| 型號： | RG82845MZ |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 72/157頁 |
| 文件大?。?/td> | 1407K |
| 代理商： | RG82845MZ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁當(dāng)前第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
21
R
2.1.
Host Interface Signals
Table 4. Host Interface Signal Descriptions
Signal Name
Type
Description
ADS#
I/O
AGTL+
Address Strobe: The system bus owner asserts ADS# to indicate the first of two
cycles of a request phase.
BNR#
I/O
AGTL+
Block Next Request: Used to block the current request bus owner from issuing a
new request. This signal is used to dynamically control the system bus pipeline
depth.
BPRI#
O
AGTL+
Bus Priority Request: The MCH-M is the only Priority Agent on the system bus. It
asserts this signal to obtain the ownership of the address bus. This signal has
priority over symmetric bus requests and will cause the current symmetric owner to
stop issuing new transactions unless the HLOCK# signal was asserted.
BR0#
I/O
AGTL+
Bus Request 0#: The MCH-M pulls the processor bus’ BR0# signal low during
CPURST#. The signal is sampled by the processor on the active-to-inactive
transition of CPURST#. The minimum setup time for this signal is 4 HCLKs. The
minimum hold time is 2 clocks and the maximum hold time is 20 HCLKs. BR0#
should be tristated after the hold time requirement has been satisfied.
CPURST#
O
AGTL+
CPU Reset: The CPURST# pin is an output from the MCH-M. The MCH-M asserts
CPURST# while RSTIN# (PCIRST# from ICH3-M) is asserted and for
approximately 1 ms after RSTIN# is deasserted. The CPURST# allows the
processor’s to begin execution in a known state.
DBSY#
I/O
AGTL+
Data Bus Busy: Used by the data bus owner to hold the data bus for transfers
requiring more than one cycle.
DEFER#
O
AGTL+
Defer Response: Signals that the MCH-M will terminate the transaction currently
being snooped with either a deferred response or with a retry response.
DBI[3:0]#
I/O
AGTL+ 4x
Dynamic Bus Inversion: Driven along with the HD[63:0]# signals. Indicates if the
associated signals are inverted or not. DBI[3:0]# are asserted such that the
number of data bits driven electrically low (low voltage) within the corresponding
16-bit group never exceeds 8.
DBI[x]#
Data Bits
DBI3#
HD[63:48]#
DBI2#
HD[47:32]#
DBI1#
HD[31:16]#
DBI0#
HD[15:0]#
DRDY#
I/O
AGTL+
Data Ready: Asserted for each cycle that data is transferred.
HA[31:3]#
I/O
AGTL+ 2x
Host Address Bus: HA[31:3]# connect to the system address bus. During
processor cycles the HA[31:3]# are inputs. The MCH-M drives HA[31:3]# during
snoop cycles on behalf of hub interface and AGP/Secondary PCI initiators.
HA[31:3]# are transferred at 2x rate. Note that the address is inverted on the
system bus.
HADSTB[1:0]#
I/O
AGTL+ 2x
Host Address Strobe: The source synchronous strobes used to transfer
HA[31:3]# and HREQ[4:0]# at the 2x transfer rate.
Strobe
Address Bits
HADSTB0#
HA[16:3]#, HREQ[4:0]#
HADSTB1#
HA[31:17]#
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RG82870P2 | Controller Miscellaneous - Datasheet Reference |
| RH5RE36AA-T1-FA | 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3 |
| RH5RE56AA-T1-FA | 5.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3 |
| RE5RE36AA-TZ-FC | 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PBCY3 |
| RE5RE36AC-TZ-FC | 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PBCY3 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RG82845PE S L6H5 | 制造商:Intel 功能描述:CHIPSTGMCH 82845PE HT-PBGA760 |
| RG82845PESL6Q3 | 制造商:Intel 功能描述:Chipsets |
| RG82845-SL5V7 | 制造商:Intel 功能描述:INTEL 845G GRAPHICS AND MEMORY CONTROLLER HUB(GMCH) |
| RG82845SL5YQ | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel?? 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR |
| RG82845-SL63W | 制造商:Intel 功能描述:INTEL 845G GRAPHICS AND MEMORY CONTROLLER HUB(GMCH) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。