參數(shù)資料
型號: RH80532GC029512
元件分類: 微處理器
英文描述: Microprocessor
中文描述: 微處理器
文件頁數(shù): 10/93頁
文件大?。?/td> 2353K
代理商: RH80532GC029512
Mobile Intel
Pentium
4 Processor-M
10
Datasheet
250686-002
1.8 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in
Battery Optimized Mode at 1.20 V)
1.7 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in
Battery Optimized Mode at 1.20 V)
1.6 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in
Battery Optimized Mode at 1.20 V)
1.5 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in
Battery Optimized Mode at 1.20 V)
1.4 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in
Battery Optimized Mode at 1.20 V)
1.1
Terminology
A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as
address
or
data
), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a
hex ‘A’, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
“System Bus” refers to the interface between the processor and system core logic (a.k.a. the chipset
components). The system bus is a multiprocessing interface to processors, memory, and I/O.
1.1.1
Terminology
Commonly used terms are explained here for clarification:
Processor
— For this document, the term processor shall mean the Mobile Intel Pentium 4
Processor-M in the 478-pin package.
Keep out zone
— The area on or near the processor that system design can not utilize.
Intel
845MP/845MZ chipsets
— Mobile chipsets that will support the Mobile Intel Pentium
4 Processor-M.
Processor core
— Mobile Intel Pentium 4 Processor-M core die with integrated L2 cache.
Micro-FCPGA
package
— Micro Flip-Chip Pin Grid Array package with 50-mil pin pitch.
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