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250686-002
Datasheet
5
Mobile Intel
Pentium
4 Processor-M
Figures
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VCCVID Pin Voltage and Current Requirements................................................14
Typical VCCIOPLL, VCCA, VSSA Power Distribution ........................................16
Phase Lock Loop (PLL) Filter Requirements .....................................................17
Illustration of VCC Static and Transient Tolerances (VID = 1.30 V)....................25
Illustration of VCC Static and Transient Tolerances (VID = 1.20 V)....................27
Illustration of Deep Sleep VCC Static and Transient Tolerances (VID Setting
= 1.30 V)..............................................................................................................28
ITPCLKOUT[1:0] Output Buffer Diagram............................................................33
AC Test Circuit....................................................................................................40
TCK Clock Waveform..........................................................................................40
Differential Clock Waveform................................................................................41
Differential Clock Crosspoint Specification..........................................................42
System Bus Common Clock Valid Delay Timings...............................................42
System Bus Reset and Configuration Timings....................................................43
Source Synchronous 2X (Address) Timings .......................................................43
Source Synchronous 4X Timings........................................................................44
Test Reset Timings .............................................................................................45
Power Up Sequence ..........................................................................................45
Power Down Sequence.......................................................................................45
THERMTRIP# to Vcc Timing...............................................................................46
FERR#/PBE# Valid Delay Timing .......................................................................46
TAP Valid Delay Timing ......................................................................................46
ITPCLKOUT Valid Delay Timing.........................................................................47
Stop Grant/Sleep/Deep Sleep Timing.................................................................47
Enhanced Intel SpeedStep Technology/Deep Sleep Timing ..............................48
BCLK Signal Integrity Waveform.........................................................................50
Low-to-High System Bus Receiver Ringback Tolerance.....................................51
High-to-Low System Bus Receiver Ringback Tolerance.....................................51
Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and
TAP Buffers.........................................................................................................52
High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and
TAP Buffers.........................................................................................................52
Maximum Acceptable Overshoot/Undershoot Waveform ...................................57
Micro-FCPGA Package Top and Bottom Isometric Views..................................58
Micro-FCPGA Package - Top and Side Views....................................................59
Micro-FCPGA Package - Bottom View................................................................61
The Coordinates of the Processor Pins as Viewed From the Top of the
Package. .............................................................................................................62
Clock Control States............................................................................................90
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