參數(shù)資料
型號(hào): RH80532GC029512
元件分類: 微處理器
英文描述: Microprocessor
中文描述: 微處理器
文件頁數(shù): 19/93頁
文件大?。?/td> 2353K
代理商: RH80532GC029512
Mobile Intel
Pentium
4 Processor-M
250686-002
Datasheet
19
2.6
System Bus Signal Groups
In order to simplify the following discussion, the system bus signals have been combined into
groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as
a reference level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as
well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+
output group as well as the AGTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals which are dependant upon the rising edge
of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals
which are relative to their respective strobe lines (data and address) as well as the rising edge of
BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at
any time during the clock cycle.
Table 3
identifies which signals are common clock, source
synchronous, and asynchronous.
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