參數(shù)資料
型號(hào)： RH80532GC029512
元件分類(lèi)： 微處理器
英文描述： Microprocessor
中文描述： 微處理器
文件頁(yè)數(shù)： 82/93頁(yè)
文件大?。?/td> 2353K
代理商： RH80532GC029512
Mobile Intel
Pentium
4 Processor-M Datasheet
82
Datasheet
250686-002
LOCK#
Input/
Output
LOCK# indicates to the system that a transaction must occur atomically. This signal
must connect the appropriate pins of all processor system bus agents. For a locked
sequence of transactions, LOCK# is asserted from the beginning of the first
transaction to the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the processor
system bus, it will wait until it observes LOCK# deasserted. This enables symmetric
agents to retain ownership of the processor system bus throughout the bus locked
operation and ensure the atomicity of lock.
MCERR#
Input/
Output
MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error
without a bus protocol violation. It may be driven by all processor system bus
agents.
MCERR# assertion conditions are configurable at a system level. Assertion options
are defined by the following options:
Enabled or disabled.
Asserted, if configured, for internal errors along with IERR#.
Asserted, if configured, by the request initiator of a bus transaction after it
observes an error.
Asserted by any bus agent when it observes an error in a bus transaction.
For more details regarding machine check architecture, please refer to the
IA-32
Software Developer’s Manual, Volume 3: System Programming Guide
.
PROCHOT#
Output
The assertion of PROCHOT# (Processor Hot) indicates that the processor die
temperature has reached its thermal limit. See Section 6 for more details.
PWRGOOD
Input
PWRGOOD (Power Good) is a processor input. The processor requires this signal
to be a clean indication that the clocks and power supplies are stable and within
their specifications. ‘Clean’ implies that the signal will remain low (capable of
sinking leakage current), without glitches, from the time that the power supplies are
turned on until they come within specification. The signal must then transition
monotonically to a high state.
Figure 16
illustrates the relationship of PWRGOOD to
the RESET# signal. PWRGOOD can be driven inactive at any time, but clocks and
power must again be stable before a subsequent rising edge of PWRGOOD. It
must also meet the minimum pulse width specification in
Table 21
, and be followed
by a 1 to 10 ms RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
REQ[4:0]#
Input/
Output
REQ[4:0]# (Request Command) must connect the appropriate pins of all processor
system bus agents. They are asserted by the current bus owner to define the
currently active transaction type. These signals are source synchronous to
ADSTB0#. Refer to the AP[1:0]# signal description for details on parity checking of
these signals.
RESET#
Input
Asserting the RESET# signal resets the processor to a known state and invalidates
its internal caches without writing back any of their contents. For a power-on Reset,
RESET# must stay active for at least one millisecond after V
CC
and BCLK have
reached their proper specifications. On observing active RESET#, all system bus
agents will deassert their outputs within two clocks. RESET# must not be kept
asserted for more than 10 ms while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the
Section 7.1
.
This signal does not have on-die termination and must be terminated on the
system board.
RS[2:0]#
Input
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the
appropriate pins of all processor system bus agents.
Table 36. Signal Description (Page 6 of 8)
Name
Type
Description
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