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參數(shù)資料
| 型號(hào)： | RS5C62 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | REAL-TIME CLOCK |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁(yè)數(shù)： | 10/48頁(yè) |
| 文件大?。?/td> | 419K |
| 代理商： | RS5C62 |
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6
RP/RF/RS5C62
FUNCTIONAL DESCRIPTION
1. Addressing
Address Bus
BANK 0 (BANK=0)
BANK 1 (BANK=1)
A3
A2 A1 A0
Description
D3
D2
D1
D0
Description
D3
D2
D1
D0
0
0
0
0
0
1 sec. Counter
R/W
S
8
S
4
S
2
S
1
Cyclic interrupt select Reg.
W/O
CT
3
CT
2
CT
1
CT
0
1
0
0
0
1
10 sec. Counter
R/W
S
40
S
20
S
10
Adust Reg.
W/O
ADJ
2
0
0
1
0
1 min. Counter
R/W
M
8
M
4
M
2
M
1
1 min. alarm Reg.
R/W
AM
8
AM
4
AM
2
AM
1
3
0
0
1
1
10 min. Counter
R/W
M
40
M
20
M
10
10 min. alarm Reg.
R/W
AM
40
AM
20
AM
10
4
0
1
0
0
1 hour Counter
R/W
H
8
H
4
H
2
H
1
1 hour alarm Reg.
R/W
AH
8
AH
4
AH
2
AH
1
5
0
1
0
1
10 hour Counter
R/W
P/A
or H
20
H
10
10 hour alarm Reg.
R/W
AP/A
or AH
20
AH
10
6
0
1
1
0
day-of-the-week Counter
R/W
W
4
W
2
W
1
7
0
1
1
1
1 day Counter
R/W
D
8
D
4
D
2
D
1
8
1
0
0
0
10 day Counter
R/W
D
20
D
10
9
1
0
0
1
1 month Counter R/W
MO
8
MO
4
MO
2
MO
1
A
1
0
1
0
10 month Counter
R/W
MO
10
12/24 select Reg.
W/O
12/24
B
1
0
1
1
1 year Counter
R/W
Y
8
Y
4
Y
2
Y
1
Leap Year Reg.
R/O
R/W
LY
1
LY
0
LYE
W/O
TM
2
TM
1
TM
0
C
1
1
0
0
10 year Counter
R/W
Y
80
Y
40
Y
20
Y
10
Timer Clock Select Reg.
R/W
TM
3
R/O
TMFG
D
1
1
0
1
Control Reg. 1
W/O WTEN ALEN
TMR
BANK Control Reg. 1
W/O WTEN ALEN
TMR
BANK
E
1
1
1
0
Control Reg. 2
R/O
R/W
BSY
Control Reg. 2
R/O
R/W
BSY
CTFG
ALFG
XSTP
CTFG
ALFG
XSTP
F
1
1
1
1
Control Reg. 3
W/O TSTA
TSTB
WTRST
Control Reg. 3
W/O TSTA
TSTB
WTRST
*
1) R/W bits can be read and written. R/O bits can only be read. W/O bits can only be written.
*
2) It is no problem to attempt writing to R/O bits and blank bits, but the attempt will fail.
*
3) If W/O bits and blank bits are read, the returned value is 0.
*
4) The control registers 1, 2, and 3 have the same address assignment for BANK0 and BANK1.
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