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參數(shù)資料
| 型號： | RS5C62 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | REAL-TIME CLOCK |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁數(shù)： | 26/48頁 |
| 文件大?。?/td> | 419K |
| 代理商： | RS5C62 |
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RP/RF/RS5C62
5. Interrupts
Interrupts are available in the following two types:
1) Alarm interrupt: Requested upon driving low (turning on) the INTR pin in matching between preset alarm time
(in minutes and hours) and time indicated by the time counter (in minutes and hours).
2) Cyclic interrupt: Requested upon driving low (turning on) the INTR pin with a preset cycle.
To output an alarm interrupt and a cyclic interrupt, the INTR pin is configured as shown in the figure below:
*
1) When an alarm interrupt and a cyclic interrupt are generated in combination, their logical sum (OR) is output from the INTR pin. In this event, they
can be distinguished from each other by reading the ALFG and CTFG bits of the control register 2.
*
2) The INTR pin output has indefinite states at power-on from 0V.
*
3) An alarm interrupt and a cyclic interrupt are both enabled whether the CE pin input is held high or low.
*
1) The above figure assumes that an alarm interrupt occurs in the absence of a cyclic interrupt.
*
2) The ALFG bit has an inverse logic from that of the INTR pin output.
INTR
Alarm interrupt
Cyclic interrupt
5.1 Alarm Interrupt
Desired alarm time (in minutes and hours) can be preset in the alarm digits of the alarm register with the ALEN
bit set to “0” and then to “1” in the control register 1. Upon matching between the preset alarm time and the time
indicated by the time counter, the INTR pin is driven low (turned on) to output a request for an alarm interrupt.
The INTR pin output can be controlled by using the ALEN bit in the control register 1 and the ALFG bit in the con-
trol register 2.
ALEN=1
ALEN=1
ALEN=0
ALFG=0
ALEN=1
ALEN=0
Alarm time match
Alarm time match
Alarm time match
Alarm time match
INTR
MAX.61.1μs
INTR
Alarm time match period: 1 minute
Alarm-time................Alarm register
(See
“
2. 6 Alarm Register”.)
(See “2. 1 Control Register 1”.)
(See “2. 2 Control Register 2”.)
(See “2. 5 Control Register 2”.)
(See “2. 2 Control Register 2”.)
ALEN bi
ALFG bit
Cyclic.......................Cyclic interrupt select register
CTFG bit
Interrupt Registers
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