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參數(shù)資料
| 型號： | RS5C62 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | REAL-TIME CLOCK |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁數(shù)： | 14/48頁 |
| 文件大?。?/td> | 419K |
| 代理商： | RS5C62 |
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10
RP/RF/RS5C62
2.3 Control Register 3 (BANK0/1 at “Fh”)
D3
D2
D1
D0
*
*
1
0
0
0
0
(For write operation)
(For read operation)
*
2
Bit for resetting lower-order counter than the second counter. *
3
WTRST
Function
0
1
Specifies normal operation.
Specifies resetting of 1- to 8-Hz dividers conditional on restart.
TSTA,TSTB
Function
0
1
Specifies setting of the test mode.
Specifies setting of normal operation.
Test mode setting bits *
4
TSTA
TSTB
WTRST
*
1) The bit marked with “
*
” is not intended for write operation.
*
2) This bit is intended for only write operation and always read as “0”.
*
3) When set to “1”, the WTRST bit specifies resetting of the lower-order counter than the 1 second counter ranging from 8Hz and 4Hz to 2Hz and 1Hz
conditional on restart. The WTRST bit is used to adjust the lower-order counter than the 1 second counter. After the WTRST bit is set to “1”, the
BSY bit is set to “1” for a maximum of 122.1μs.
*
4) Both the TSTA and TSTB bits must be set to “1” to specify normal operation and will automatically be set to “1” upon driving low the CE pin.
2.4 Adjustment Register (BANK1 at “1h”)
D3
D2
*
D1
*
D0
0
0
0
0
(For write operation)
(For read operation)
*
2
Second digit adjustment bit *
3
Function
0
1
Specifies normal operation.
Specifies adjustment of second digit.
*
*
1
ADJ
ADJ
*
1) The bits marked with “
*
” are not intended for write operation.
*
2) This bit is intended for only write operation and always read as “0”.
*
3) The ADJ bit is used to correct the second digit. When set to “1”, the ADJ bit functions as follows:
1) For digits ranging from 00 seconds to 29 seconds
Resets the lower-order counter than the 1 second counter (in the same manner as the
WTRST bit) and sets the second digit to “00”.
2) For digits ranging from 30 seconds to 59 seconds
Resets the second and lower-order counters (in the same manner as the WTRST bit), sets
the second digit to “00” and increments the minute digit by 1. The BSY bit is set to “1” for a maximum of 122.1μs after the ADJ bit is set to “1”.
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