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參數(shù)資料
| 型號： | RS5C62 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | REAL-TIME CLOCK |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁數(shù)： | 13/48頁 |
| 文件大?。?/td> | 419K |
| 代理商： | RS5C62 |
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RP/RF/RS5C62
*
4) The CTFG bit is set to “1” upon output of a cyclic interrupt from the INTR pin (while it is held low).
(A cyclic interrupt may occur in the pulse mode and the level mode.)
ALFG
INTR
Alarm time match
Alarm time match
Setting the ALFG
bit to “0”
Alarm time match
CTFG
INTR
CTFG
INTR
Interrupt
Preset interrupt cycle
Setting the CTFG bit to “0”
Interrupt
*
5) When the BSY bit is set to “1”, write operation must not be performed upon the time and calendar counters which are being updated. Normally, read
operation must be performed from the counters upon setting the BSY bit to “0”. Reading from them without checking the BSY bit requires separate
software for preventing reading errors. The BSY bit is set to “1” in the four cases below:
Setting the ADJ bit to “1”
Setting the WTEN bit to “1”
Setting the WTRST bit to “1”
Completion of reset
Completion of pulse for carry to second digit
Completion of correction by +1
Completion of adjustment
MAX.122.1μs
MAX.122.1μs
MAX.122.1μs
30.5μs
91.6μs
Pulse mode
(The CT
3
bit is set to “0”.)
(The CTFG bit is not intended for write
operation.)
Level mode
(The CT
3
bit is set to “1”.)
(The CTFG bit is intended for setting to “0”
only.)
(I) Adjustment by ±30 seconds
(II) Correction by +1
(when there is a 1-second carry in transition of the
WTEN bit from“0” to“1”)
(III)Normal 1-second carry
(IV)Counter resetting (setting of WTRST bit)
(Resetting the 1 to 8Hz dividers)
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