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參數(shù)資料
| 型號： | RS5C62 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | REAL-TIME CLOCK |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁數(shù)： | 37/48頁 |
| 文件大小： | 419K |
| 代理商： | RS5C62 |
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RP/RF/RS5C62
33
11.4 Adjusting Second Digit by ±30 Seconds
BANK
1
ADJ
1
*
1
*
2
*
1) Upon setting the ADJ bit to “1” in the adjustment register, the second and
lower-order 1 to 8Hz dividers are reset conditional on restart. At this
time, when the INTR pin is held low for output of a cyclic interrupt with a
cycle of 1 second or 60 seconds in the pulse mode, the INTR pin is
turned off with the timing shown below:
11.5 Detecting Start of Oscillation
NO
YES
XSTP=0
*
1
*
2
*
3
Wait
Detect start of
oscillation
Power-on from 0V
0
XSTP
*
1) This typical process of detecting the start of oscillation is applied at pow-
er-on from 0V.
*
2) At power-on from 0V, the XSTP bit is set to “1” in the control register 2.
*
3) Note that the start of oscillation normally requires a time period (oscilla-
tion start time) on the order of 0.1 to 2 seconds. Further, assign a time-
out period to exit from loop for checking the XSTP bit in the control regis-
ter 2.
L
OFF
Maximum of 200 μs
Setting the ADJ
bit to “1”
INTR
*
2) Adjustment of the second digit by ±30 seconds requires a maximum of
122.1μs, during which the BSY bit is kept at “1” in the control register 2.
Notice
In using the XSTP bit, ensure error-free detection of the stop of oscillation by:
1) Preventing the crystal oscillators causing condensation.
2) Preventing the VDD pin input from making instantaneous power disconnection.
3) Preventing the crystal oscillators from causing noises on the PCB (by such means as signal line isolation).
4) Preventing the individual pins from being impressed with voltage exceeding the maximum rating.
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