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參數(shù)資料
| 型號(hào)： | RS5C62 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | REAL-TIME CLOCK |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁數(shù)： | 21/48頁 |
| 文件大?。?/td> | 419K |
| 代理商： | RS5C62 |
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17
RP/RF/RS5C62
USAGE
1. Reading and Writing Operations
CE
Address
Reading operation
Writing operation
Data bus
A3 to A0
D3 to D0
CS
WR
RD
Upon driving high the CE pin, the interfacing input/out-
put pins are enabled, establishing equivalence in logic
between the RD and CS pin inputs during read opera-
tion and between the WR and CS pin inputs during
write operation. Upon driving low the CE pin, the inter-
facing input/output pins are disabled, preventing occur-
rence of invalid leak current due to their floating. The
CE pin must always be driven either high or low and
must never be left floating.
1.1 Reading Operation
The requirements for reading data from the internal registers and counters are: [1] holding the CE pin high, [2]
performing the process of addressing through the A3 to A0 pin inputs, then [3] driving low the CS pin, [4] causing
the RD pin to transition from its high to low levels, and thereby [5] causing the D3 to D0 pins to output read data.
The reading timing is shown in the chart below.
CE
A0 to A3
D0 to D3
(Read Data)
t
CEH
t
CES
Valid
t
AH(RD)
t
AS(RD)
t
RZ
t
RR
or
CS
RD
RD
CS
[1]
[2]
[3]
[4]
[5]
*
1) The CS and RD pin inputs are interchangeable. The diagonally shaded sections marked in the above timing chart may be set to both high and low
levels. (Consequently, the CS and RD pin inputs may be caused to transition from their high to low levels before the process of addressing.)
*
2) “
t
AS
(RD)” indicates the time required to perform the process of addressing before the start of read operation at which both the RD and CS pin inputs
are driven low.
*
3) “
t
AH
(RD)”indicates the time required to maintain the result of addressing after the completion of read operation at which either the RD or CS pin input
is driven high.
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