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參數(shù)資料
| 型號： | S1C7XXXF00E199 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 90 MHz, RISC MICROCONTROLLER, PQFP |
| 文件頁數(shù)： | 139/196頁 |
| 文件大?。?/td> | 1650K |
| 代理商： | S1C7XXXF00E199 |
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5 INSTRUCTION SET
S1C17 FAMILY S1C17 CORE MANUAL
EPSON
5-21
5.8.2 Delayed Branch Instructions
The S1C17 Core uses pipelined instruction processing, in which instructions are executed while other instructions
are being fetched. In a branch instruction, because the instruction that follows it has already been fetched when it is
executed, the execution cycles of the branch instruction can be reduced by one cycle by executing the prefetched in-
struction before the program branches. This is referred to as a delayed branch function, and the instruction executed
before branching (i.e., the instruction at the address next to the branch instruction) is referred to as a delayed slot
instruction.
The delayed branch function can be used in the instructions listed below, which in mnemonics is identified by the
extension “.d” added to the branch instruction name.
Delayed branch instructions
jrgt.d
jrge.d
jrlt.d
jrle.d
jrugt.d
jruge.d
jrult.d
jrule.d
jreq.d
jrne.d
call.d
calla.d
jpr.d
jpa.d
ret.d
reti.d
Delayed slot instructions
All instructions other than those listed below can be used as a delayed slot instruction.
Instructions that cannot be used as a delayed slot instruction
brk
call
calla
ext
halt
int
jpa
jpr
jr*
ret
retd
reti
slp
The ext instruction cannot be used to expand the operand of delayed slot instructions.
A delayed slot instruction is always executed regardless of whether the delayed branch instruction used is con-
ditional or unconditional and whether it branches.
In “non-delayed” branch instructions (those not followed by the extension “.d”), the instruction at the address
next to the branch instruction is not executed if the program branches; however, if it is a conditional jump and
the program does not branch, the instruction at the next address is executed as the one that follows the branch
instruction.
The return address saved to the stack by the call.d or calla.d instruction becomes the address for the next
instruction following the delayed slot instruction, so that the delayed slot instruction is not executed when the
program returns from the subroutine.
No interrupts occur in between a delayed branch instruction and a delayed slot instruction, as they are masked
out by hardware.
Application for leaf subroutines
The following shows an example application of delayed branch instructions for achieving a fast leaf subroutine
call.
Example:
jpr.d
SUB
; Jumps to a subroutine by a delayed branch instruction
ld.a
%r7,%pc ; Loads the return address into a general-purpose register by
; a delayed slot instruction
add.a
%r1,%r2 ; Return address
:
SUB:
:
jpr
%r7
; Return
Notes: The ld.a %rd,%pc instruction must be executed as a delayed slot instruction. If it does not
follow a delayed branch instruction, the PC value that is loaded into the rd register may not be
the next instruction address to the ld.a instruction.
The delayed branch instruction listed below can only be used with the ld.a %rd,%pc de-
layed slot instruction.
- jpr.d
%rb/sign10
- jr*.d
sign7
- jpa.d
%rb/imm7
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