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參數(shù)資料
| 型號： | S1C7XXXF00E199 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 90 MHz, RISC MICROCONTROLLER, PQFP |
| 文件頁數(shù)： | 151/196頁 |
| 文件大小： | 1650K |
| 代理商： | S1C7XXXF00E199 |
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6 FUNCTIONS
6-8
EPSON
S1C17 FAMILY S1C17 CORE MANUAL
6.3.5 Address Misaligned Interrupt
The load instructions that access memory or I/O areas are characteristic in that the data size to be transferred is
predetermined for each instruction used, and that the accessed addresses must be aligned with the respective data-
size boundaries.
Instruction
Transfer data size
Address
ld.b/ld.ub
Byte (8 bits)
Byte boundary (applies to all addresses)
ld
16 bits
16-bit boundary (least significant address bit = 0)
ld.a
32 bits
32-bit boundary (two least significant address bits = 00)
If the specified address in a load instruction does not satisfy this condition, the processor assumes an address
misaligned interrupt and performs interrupt handling. Even in this case the load instruction is executed as the least
significant bit or the two low-order bits of the address set to 0. The PC value saved to the stack in interrupt handling
is the address of the load instruction that caused the interrupt.
This interrupt does not occur in the program branch instructions as the least significant bit of the PC is always fixed
to 0. The same applies to the vector for interrupt handling.
6.3.6 NMI
An NMI is generated when the nmi_n input on the processor is asserted low. When an NMI occurs, the processor
performs interrupt handling after it has finished executing the instruction currently underway.
6.3.7 Maskable External Interrupts
The S1C17 Core can accept up to 32 types of maskable external interrupts (however, the first three interrupt causes
use the save vector address as the reset interrupt, address misaligned interrupt, and NMI). It is only when the IE
(interrupt enable) flag in the PSR is set that the processor accepts a maskable external interrupt. Furthermore, their
acceptable interrupt levels are limited by the IL (interrupt level) field in the PSR. The interrupt levels (0–7) in the
IL field dictate the interrupt levels that can be accepted by the processor, and only interrupts with priority levels
higher than that are accepted. Interrupts with the same interrupt level as IL cannot be accepted.
The IE flag can be set in the software. When an interrupt occurs, the IE flag is cleared to 0 (interrupts disabled)
after the PSR is saved to the stack, and the maskable interrupts remain disabled until the IE flag is set in the handler
routine or the handler routine is terminated by the reti instruction that restores the PSR from the stack. The IL
field is set to the priority level of the interrupt that occurred.
Multiple interrupts or the ability to accept another interrupt during interrupt handling if its priority is higher than
that of the currently serviced interrupt can easily be realized by setting the IE flag in the interrupt handler routine.
When the processor is reset, the PSR is initialized to 0 and the maskable interrupts are therefore disabled, and the
interrupt level is set to 0 (interrupts with priority levels 1–7 enabled).
The following describes how the maskable interrupts are accepted and processed by the processor.
(1) Suspends the instructions currently being executed.
The interrupt is accepted synchronously with the rising edge of the system clock at the end of the cycle of the
currently executed instruction.
(2) Saves the contents of the PC (current value) and PSR to the stack (SP), in that order.
(3) Clears the IE flag in the PSR and copy the priority level of the accepted interrupt to the IL field.
(4) Reads the vector for the interrupt from the vector address in the vector table, and sets it in the PC. The processor
then branches to the interrupt handler routine.
In the interrupt handler routine, the reti instruction should be executed at the end of processing. In the reti
instruction, the saved data is restored from the stack in order of the PC and PSR, and the processing returns to the
suspended instructions.
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