6 FUNCTIONS
S1C17 FAMILY S1C17 CORE MANUAL
EPSON
6-1
6 Functions
This chapter describes the processing status of the S1C17 Core and outlines the operation.
6.1 Transition of the Processor Status
The diagram below shows the transition of the operating status in the S1C17 Core.
Program execution state
Interrupt
handling
Debug
interrupt
handling
SLEEP mode
Reset state
HALT mode
slp
instruction
Interrupt
Debug
interrupt
retd
instruction
Interrupt
reti
instruction
halt
instruction
Interrupt
Figure 6.1.1 Processor Status Transition Diagram
6.1.1 Reset State
The processor is initialized when the reset signal is asserted, and then starts processing from the reset vector when
the reset signal is deasserted.
6.1.2 Program Execution State
This is a state in which the processor executes the user program sequentially. The processor state transits to another
when an interrupt occurs or the slp or halt instruction is executed.
6.1.3 Interrupt Handling
When a software or other interrupt occurs, the processor enters an interrupt handling state. The following are the
possible causes of the need for interrupt handling:
(1) External interrupt
(2) Software interrupt
(3) Address misaligned interrupt
(4) NMI
6.1.4 Debug Interrupt
The S1C17 Core incorporates a debugging assistance facility to increase the efficiency of software development. To
use this facility, a dedicated mode known as “debug mode” is provided. The processor can be switched from user
mode to this mode by the brk instruction or a debug interrupt. The processor does not normally enter this mode.
6.1.5 HALT and SLEEP Modes
The processor is placed in HALT or SLEEP mode to reduce power consumption by executing the halt or slp
instruction in the software (see Section 6.4). Normally the processor can be taken out of HALT or SLEEP mode by
NMI or an external interrupt as well as initial reset.