2 REGISTERS
S1C17 FAMILY S1C17 CORE MANUAL
EPSON
2-1
2 Registers
The S1C17 Core contains eight general-purpose registers and three special registers.
R4
R5
R6
R7
R3
R2
R1
R0
bit 23
bit 0
General-purpose registers
PC
bit 23
7
6
5
4
3
2
1
0
bit 0
PSR
SP
Special registers
IL[2:0]
7
6
5
IE
4
C
3
V
2
Z
1
N
0
Figure 2.1 Registers
2.1 General-Purpose Registers (R0–R7)
Symbol
R0–R7
Size
24 bits
Initial value
0x000000 or indeterminate
Register name
General-Purpose Register
R/W
R/W
The eight registers R0–R7 (r0–r7) are 24-bit general-purpose registers that can be used for data manipulation, data
transfer, memory addressing, or other general purposes. The contents of all of these registers are handled as 24-bit
data or addresses. 8- or 16-bit data can be sign- or zero-extended to a 24-bit quantity when it is loaded into one of
these registers using a load instruction or a conversion instruction. When these registers are used for address refer-
ences, 24-bit memory space can be accessed directly.
At initial reset, the contents of the general-purpose registers are set to 0 (may be indeterminate without initialization
depending on the configuration).
2.2 Program Counter (PC)
Symbol
PC
Size
24 bits
Initial value
(Reset vector)
Register name
Program Counter
R/W
R
The Program Counter (hereinafter referred to as the “PC”) is a 24-bit counter for holding the address of an instruc-
tion to be executed. More specifically, the PC value indicates the address of the next instruction to be executed.
As the instructions in the S1C17 Core are fixed at 16 bits in length, the LSB (bit 0) of the PC is always 0.
Although the S1C17 Core allows the PC to be referenced in a program, the user cannot alter it. Note, however, that
the value actually loaded into the register when a ld.a %rd,%pc instruction (can be executed as a delayed in-
struction) is executed is the “PC value for the ld instruction + 2.”
At an initial reset, the reset vector (address) written at the top of vector table indicated by TTBR is loaded into the
PC, and the processor starts executing a program from the address indicated by the PC.
Effective address
0
1
23
Figure 2.2.1 Program Counter (PC)