參數(shù)資料
型號： S29CL016J0PFFM102
廠商： SPANSION LLC
元件分類： PROM
英文描述： 512K X 32 FLASH 3.3V PROM, 54 ns, PBGA80
封裝： 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80
文件頁數(shù)： 16/78頁
文件大?。?/td> 1825K
代理商： S29CL016J0PFFM102
September 27, 2006 S29CD-J_CL-J_00_B1
S29CD-J & S29CL-J Flash Family
21
Pr el im i n a r y
8.2
Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation, data
is read from one memory location at a time. Addresses are presented to the device in random
order, and the propagation delay through the device causes the data on its outputs to arrive
asynchronously with the address on its inputs.
The internal state machine is set for asynchronously reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory content occurs
during the power transition. No command is necessary in this mode to obtain array data. Stan-
dard microprocessor read cycles that assert valid addresses on the device address inputs
produce valid data on the device data outputs. The device remains enabled for read access until
the command register contents are altered.
The device has two control functions which must be satisfied in order to obtain data at the out-
puts. CE# is the power control and should be used for device selection (CE# must be set to VIL
to read data). OE# is the output control and should be used to gate data to the output pins if
the device is selected (OE# must be set to VIL in order to read data). WE# should remain at VIH
(when reading data).
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The
chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data
at the output pins. The output enable access time (tOE) is the delay from the falling edge of OE#
to valid data at the output pins (assuming the addresses have been stable for at least a period
of tACC-tOE and CE# has been asserted for at least tCE-tOE time). Figure 8.1 shows the timing
diagram of an asynchronous read operation.
Note: Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required.
Figure 8.1 Asynchronous Read Operation
Refer to Asynchronous Operations on page 56 for timing specifications and to Figure 18.2, Con-
ventional Read Operations Timings, on page 56 for another timing diagram. ICC1 in the DC
Characteristics table represents the active current specification for reading array data.
D0
D1
D2
D3
CE#
CLK
ADV#
Addresses
Data
OE#
WE#
IND/WAIT#
VIH
Float
VOH
Address 0
Address 1
Address 2
Address 3
Float
相關(guān)PDF資料
PDF描述
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