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參數(shù)資料
| 型號： | S29CL016J0PFFM102 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 512K X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80 |
| 文件頁數(shù)： | 26/78頁 |
| 文件大小： | 1825K |
| 代理商： | S29CL016J0PFFM102 |
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30
S29CD-J & S29CL-J Flash Family
S29CD-J_CL-J_00_B1 September27,2006
Prel imi n ary
8.7.2
Sector Erase
The sector erase function erases one or more sectors in the memory array. (See Table 20.1,
on page 31.) The device does not require the system to preprogram prior to erase. The Embed-
ded Erase algorithm automatically programs and verifies the entire memory for an all-zero data
pattern prior to electrical erase. After a successful sector erase, all locations within the erased
sector contain FFFFh. The system is not required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-out of no less than 80 s occurs.
During the time-out period, additional sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any sequence, and the number of sectors
may be from one sector to all sectors. The time between these additional cycles must be less
than 80 s. Any sector erase address and command following the exceeded time-out (80 s)
may or may not be accepted. A time-out of 80 s from the rising edge of the last WE# (or CE#)
initiates the execution of the Sector Erase com-mand(s). If another falling edge of the WE# (or
CE#) occurs within the 80 s time-out window, the timer is reset. Any command other than Sec-
tor Erase or Erase Suspend during the time-out period resets that bank to the read mode. The
system can monitor DQ3 to determine if the sector erase timer has timed out (See DQ3: Sector
Erase Timer on page 39.) The time-out begins from the rising edge of the final WE# pulse in the
command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data; ad-
dresses are no longer latched. The system can determine the status of the erase operation by
reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to Write Operation Status on page 33 for
information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored. However, note that a hardware reset immediately terminates the erase
operation. If that occurs, the sector erase command sequence should be re-initiated once that
bank has returned to reading array data, in order to ensure data integrity.
Figure 8.6 illustrates the algorithm for the erase operation. Refer to Program/Erase Operations
on page 28 for parameters and timing diagrams.
8.7.3
Chip Erase
Chip erase is a six-bus cycle operation as indicated by Command Definitions on page 71. The
Chip Erase command is used to erase the entire flash memory contents of the chip by issuing a
single command. However, chip erase does not erase protected sectors.
This command invokes the Embedded Erase algorithm, which does not require the system to pre-
program prior to erase. The Embedded Erase algorithm automatically preprograms and verifies
the entire memory for an all-zero data pattern prior to electrical erase. After a successful chip
erase, all locations of the chip contain FFFFh. The system is not required to provide any controls
or timings during these operations. Command Definitions on page 71 in the appendix shows the
address and data requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and ad-
dresses are no longer latched. The system can determine the status of the erase operation by
using DQ7, DQ6 or the RY/BY#. Refer to Write Operation Status on page 33 for information on
these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hard-
ware reset immediately terminates the erase operation. If that occurs, the chip erase command
sequence should be reinitiated once that bank has returned to reading array data, to ensure data
integrity.
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