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參數(shù)資料
| 型號(hào)： | S29CL016J0PFFM102 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 512K X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80 |
| 文件頁數(shù)： | 21/78頁 |
| 文件大?。?/td> | 1825K |
| 代理商： | S29CL016J0PFFM102 |
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26
S29CD-J & S29CL-J Flash Family
S29CD-J_CL-J_00_B1 September27,2006
Prel imi n ary
Notes:
1. Burst access starts with a rising CLK edge and when ADV# is active.
2. Configurations register 6 is always set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge.
3. CR [13-10] = 1 or three clock cycles
4. CR [13-10] = 2 or four clock cycles
5. CR [13-10] = 3 or five clock cycles
Figure 8.4 Initial Burst Delay Control
8.4.3
Configuration Register
The configuration register sets various operational parameters associated with burst mode. Upon
power-up or hardware reset, the device defaults to the asynchronous read mode and the con-
figuration register settings are in their default state. (See Table 8.6 for the default Configuration
Register settings.) The host system determines the proper settings for the entire configuration
register, and then execute the Set Configuration Register command sequence before attempting
burst operations. The configuration register is not reset after deasserting CE#.
The Configuration Register does not occupy any addressable memory location, but rather, is ac-
cessed by the Configuration Register commands. The Configuration Register is readable at any
time, however, writing the Configuration Register is restricted to times when the Embedded Al-
gorithm is not active. If the user attempts to write the Configuration Register while the
Embedded Algorithm is active, the write operation is ignored and the contents of the Configu-
ration Register remain unchanged.
The Configuration Register is a 16 bit data field which is accessed by DQ15–DQ0. During a read
operation, DQ31–DQ16 returns all zeroes. Also, the Configuration Register reads operate the
same as the Autoselect command reads. When the command is issued, the bank address is
latched along with the command. Read operations to the bank that was specified during the Con-
figuration Register read command return Configuration Register contents. Read operations to the
other bank return flash memory data. Either bank address is permitted when writing the Config-
uration Register read command.
The configuration register can be read with a four-cycle command sequence. See Command Def-
initions on page 71 for sequence details.
CLK
ADV#
Addresses
DQ31-DQ03
DQ31-DQ04
DQ31-DQ05
Valid Address
Three CLK Delay
2nd CLK
3rd CLK
4th CLK
5th CLK
1st CLK
Four CLK Delay
Address 1 Latched
Five CLK Delay
D0
D1
D2
D3
D0
D1
D2
D0
D1
D2
D3
D4
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