參數(shù)資料
型號(hào)： S29CL016J0PFFM102
廠商： SPANSION LLC
元件分類： PROM
英文描述： 512K X 32 FLASH 3.3V PROM, 54 ns, PBGA80
封裝： 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80
文件頁數(shù)： 57/78頁
文件大?。?/td> 1825K
代理商： S29CL016J0PFFM102
58
S29CD-J & S29CL-J Flash Family
S29CD-J_CL-J_00_B1 September27,2006
Prel imi n ary
18.3 Synchronous Operations
Notes:
1.
Using the max tAAVS and min tADVCS specs together will result in incorrect data output.
2. Not 100% tested
3. Recommended 50% Duty Cycle
Table 18.3 Burst Mode Read for 32 Mb and 16 Mb
Parameter
Description
Speed Options
Unit
JEDEC
Std.
75MHz, OR 66MHz, OP 56MHz, OM 40MHz, OJ
tBACC
Burst Access Time Valid Clock to Output Delay
Max
7.5 FBGA
8
ns
tADVCS ADV# Setup Time to Rising Edge of CLK
Min
6
ns
tADVCH ADV# Hold Time from Rising Edge of CLK
Min
1.5
ns
tADVP
ADV# Pulse Width
Min
7.5
8.5
9.5
10.5
ns
tBDH
Valid Data Hold from CLK (Note 2)
Min
2
3
ns
tINDS
CLK to Valid IND/WAIT# (Note 2)
Max
7.5 FBGA
9 FBGA
9.5 PQFP
10 FBGA
10 PQFP
17
ns
tINDH
IND/WAIT# Hold from CLK (Note 2)
Min
2
3
ns
tIACC
ADV or ADD Valid (Whichever Occurs Last) to Valid
Data Out, Initial Burst Access
Max
48
54
ns
tCLK
CLK Period
Min
13.3
15.15
17.85
25
ns
Max
60
tCR
CLK Rise Time (Note 2)
Max
3
ns
tCF
CLK Fall Time (Note 2)
Max
3
ns
tCLKH
CLK High Time (Note 3)
Min
6.65
6.8
8.0
11.25
ns
tCLKL
CLK Low Time (Note 3)
Min
6.65
27
ns
tOE
Output Enable to Output Valid
Max
20
ns
tDF
tOEZ
Output Enable to Output High Z (Note 2)
Min
2
3
ns
Max
7.5
10
15
17
tEHQZ
tCEZ
Chip Enable to Output High Z (Note 2)
Max
7.5
10
15
17
ns
tCES
CE# Setup Time to Clock
Min
4
5
6
ns
tAAVS
ADV# Falling Edge to Address Valid (Note 1)
Max
6.5
ns
tAAVH
Address Hold Time from Rising Edge of AVD#
Min
15
ns
tRSTZ
RESET# Low to Output High Z (Note 2)
Max
7.5
10
15
17
ns
tWADVH1 ADV# Falling Edge to WE# Falling Edge
Min
5
ns
tWADVH2 ADV# Rising Edge to WE# Rising Edge
Min
10
ns
相關(guān)PDF資料
PDF描述
S29CL016J1JFFM112 512K X 32 FLASH 3.3V PROM, 54 ns, PBGA80
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