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參數(shù)資料
| 型號(hào)： | SAA1575HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Global Positioning System (GPS)baseband processor(通用定位系統(tǒng)基帶處理器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, SOT-407-1, LQFP-100 |
| 文件頁數(shù)： | 13/56頁 |
| 文件大?。?/td> | 744K |
| 代理商： | SAA1575HL |
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1999 Jun 04
13
Philips Semiconductors
Product specification
Global Positioning System (GPS)
baseband processor
SAA1575HL
7.4
Memory organization
The memory space in the SAA1575HL is configured in a
Harvard architecture which means that the code and data
memory are organized in separate address spaces. This
section describes the SAA1575HL memory requirements.
7.4.1
D
ATA MEMORY SPACE
The SAA1575HL contains 2 kbytes words of internal data
memory. For correct firmware operation, a further
32 kbytes words of external data memory is needed with a
maximum access time of 100 ns.
The specifications of this external memory are firmware
dependent. The figures given in this document are for the
standard Philips firmware. With other revisions of firmware
the timings could differ by integer numbers of XTAL1 clock
cycles.
In the SAA1575HL, all of the data read and write cycles are
preceded by an internal Arithmetic and Logic Elements
(ALEs) cycle (as in any standard 80C51 system).
The multiplexed address/data bus and the ALE signal are
not available externally. However, for clarity, these are
illustrated in Figs 3 to 6.
Fig.3 Example of external data read (standard firmware).
The timing is configurable under firmware control.
handbook, full pagewidth
MHB462
DMCS
RD
address bus
address/
data
ALE
internal
signals
XTAL1
address
external data
address
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