參數(shù)資料
型號: SAA1575HL
廠商: NXP SEMICONDUCTORS
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Global Positioning System (GPS)baseband processor(通用定位系統(tǒng)基帶處理器)
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, SOT-407-1, LQFP-100
文件頁數(shù): 30/56頁
文件大?。?/td> 744K
代理商: SAA1575HL
1999 Jun 04
30
Philips Semiconductors
Product specification
Global Positioning System (GPS)
baseband processor
SAA1575HL
11 AC CHARACTERISTICS
V
CC(P)
= V
CC(B)
= 5 V; V
CC(core)
= V
CC(R)
= 3 V; T
amb
= 20
°
C; f
osc
= 30 MHz; standard Philips firmware (release HD00);
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
External clock
f
osc
T
clk
t
CLKH
t
CLKL
t
r(clk)
t
f(clk)
f
clk(ref)
oscillator frequency
clock period and CPU timing cycle
clock HIGH time
clock LOW time
clock rise time
clock fall time
reference clock frequency
26
30
33.3
6.7
6.7
5
5
14.4
32
35
MHz
ns
ns
ns
ns
ns
MHz
40 to 60% duty cycle
40 to 60% duty cycle
External program memory read (non-burst code read);
see Fig.16
t
AVAU
t
AVPL
t
W(PMCS)
t
PLIV
t
h(I)
t
AVIV
t
su(I)
address valid time period
address valid to PMCS asserted
PMCS pulse width
PMCS LOW to instruction valid
instruction hold time after PMCS de-asserted
address valid to instruction valid (access time)
instruction set-up time before PMCS
de-asserted
bus 3-state after PMCS de-asserted
hold time of a (3 : 1) after PMCS de-asserted
163.7
62.7
97.0
0.0
14.0
165.7
65.7
98.0
82.0
148.7
16.0
85.0
151.7
ns
ns
ns
ns
ns
ns
ns
t
PXIZ
t
h
0.0
30.0
1.0
36.0
ns
ns
External program memory read (burst code read);
see Figs 16 and 17
t
AVAU
t
AVIV
t
IVAU
t
AUIU
address valid time period
address valid to instruction valid (access time)
instruction valid to address undefined
address valid to instruction undefined
131.3
15.0
0.0
132.3
115.3
17.0
118.3
ns
ns
ns
ns
External data memory read;
see Fig.18
t
AVAU
t
RLEL
t
W(DMCS)
t
RHEH
t
AVRL
t
W(RD)
t
AVDV
t
RLDV
t
su(D)
t
h(D)
t
RHDZ
address valid time period
RD asserted to DMCS asserted
DMCS pulse width
RD de-asserted to DMCS de-asserted
address valid to RD asserted
RD pulse width
address valid to data valid (access time)
RD asserted to data valid
data set-up time before RD de-asserted
data hold time after RD de-asserted
bus 3-state after RD de-asserted
163.7
97.0
64.7
98.0
15.0
0.0
164.7
2.0
98.0
2.0
65.7
148.7
82.0
16.0
30.0
4.0
6.0
151.7
85.0
36.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
note 1
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