參數(shù)資料
型號(hào)： SAA1575HL
廠商： NXP SEMICONDUCTORS
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Global Positioning System (GPS)baseband processor(通用定位系統(tǒng)基帶處理器)
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, SOT-407-1, LQFP-100
文件頁數(shù)： 7/56頁
文件大?。?/td> 744K
代理商： SAA1575HL
1999 Jun 04
7
Philips Semiconductors
Product specification
Global Positioning System (GPS)
baseband processor
SAA1575HL
A11
24
O
External memory address bus bit 11
: 19-bit address bus; used to address external
RAM and program memory
Main I/O power supply
: 2.7 to 5.5 V operating range; main supply for the periphery
in normal operation
Ground
: 0 V reference
External memory address bus bit 10
: 19-bit address bus; used to address external
RAM and program memory
External memory address bus bit 9
: 19-bit address bus; used to address external
RAM and program memory
External memory address bus bit 8
: 19-bit address bus; used to address external
RAM and program memory
Main core power supply
: 2.7 to 3.6 V only; main supply for the core in normal
operation
Ground
: 0 V reference
External memory address bus bit 7
: 19-bit address bus; used to address external
RAM and program memory
External memory address bus bit 6
: 19-bit address bus; used to address external
RAM and program memory
External memory address bus bit 5
: 19-bit address bus; used to address external
RAM and program memory
External memory address bus bit 4
: 19-bit address bus; used to address external
RAM and program memory
External memory address bus bit 3
: 19-bit address bus; used to address external
RAM and program memory
Main I/O power supply
: 2.7 to 5.5 V operating range; main supply for the periphery
in normal operation
Ground
: 0 V reference
External memory address bus bit 2
: 19-bit address bus; used to address external
RAM and program memory
External memory address bus bit 1
: 19-bit address bus; used to address external
RAM and program memory
External program memory select
: external program memory read strobe
Test pin
: tie LOW
Reset timer control
: this controls the on-chip reset timer. If this is HIGH, reset will be
de-asserted approximately 10 ms after both PWRDN and PWRFAIL go HIGH. If this
is LOW, reset will be de-asserted approximately 10
μ
s after both
PWRDN and PWRFAIL go HIGH.
Test pin
: tie LOW
Write MSB
: write strobe for external data memory; asserted for both MSB and word
write operations; input mode only used for test purposes
Write LSB
: write strobe for external data memory; asserted for both LSB and word
write operations; input mode only used for test purposes
External data read
: read strobe for external data memory; input mode only used for
test purposes
V
CC(P)
25
V
SS
A10
26
27
O
A9
28
O
A8
29
O
V
CC(core)
30
V
SS
A7
31
32
O
A6
33
O
A5
34
O
A4
35
O
A3
36
O
V
CC(P)
37
V
SS
A2
38
39
O
A1
40
O
PMCS
TP2
RSTIME
41
42
43
O
I
I
TP1
WRH
44
45
I
I/O
WRL
46
I/O
RD
47
I/O
SYMBOL
PIN
I/O
DESCRIPTION
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