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參數(shù)資料
| 型號(hào)： | SAA1575HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Global Positioning System (GPS)baseband processor(通用定位系統(tǒng)基帶處理器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, SOT-407-1, LQFP-100 |
| 文件頁數(shù)： | 19/56頁 |
| 文件大?。?/td> | 744K |
| 代理商： | SAA1575HL |
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1999 Jun 04
19
Philips Semiconductors
Product specification
Global Positioning System (GPS)
baseband processor
SAA1575HL
7.7
The external bus
The off-chip memories and the on-chip registers are on the
same address and data bus. The routing of the data and
address signals between the on-chip registers and the
off-chip memories is controlled by a block known as the
external bus interface. In addition, certain chip enable
signals are decoded within the block to reduce the amount
of external glue logic required in the complete system.
The address latch, normally required on 80C51 systems,
is implemented within the SAA1575HL. Therefore, no ALE
signal is seen outside the IC and address and data lines
are brought out on separate pins.
However, since internally there is still the need to latch the
address from a common address/data bus, signals on the
data bus will be seen to change during the address set-up
cycles.
The lower 3 external address lines are driven directly by
the XA core and are not latched. This allows ‘burst’ code
reads to be performed in which adjacent code locations
are accessed without the need for an address latch cycle.
Signals similar to those used by a standard 80C51 or XA
system are used to control the external bus activity.
Fig.10 SAA1575HL internal address and data routing.
handbook, full pagewidth
MHB469
ADDRESS
DECODER
LE
ALE
A4 to A19
D15 to D0
A3 to A1
ADDRESS
LATCH
XA
PMCS
WRH, WRL, RD
A3 to A1
D15 to D0
D15 to D0
to MMRS
ENABLE
A4 to A19
A1 to A8
PMCS
WRH, WRL, RD
DMCS
16
16
3
3
16
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