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參數(shù)資料
| 型號： | SAA5667HL/NNNN |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100 |
| 文件頁數(shù)： | 17/112頁 |
| 文件大?。?/td> | 537K |
| 代理商： | SAA5667HL/NNNN |
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2004 Sep 03
12
Philips Semiconductors
Product specication
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA56xx
8.3
RAM organisation
Figure 6 shows the internal Data RAM is organised into
two areas: Data memory and the Special Function
Registers (SFRs).
8.4
Data memory
The Data memory (see Fig.6) is 256
× 8 bits and occupies
address range 00H to FFH when using indirect addressing
and 00H to 7FH when using direct addressing. The SFRs
occupy the address range 80H to FFH and are accessible
using direct addressing only.
The lower 128 bytes of Data memory are mapped as
shown in Fig.7. The lowest 32 bytes are grouped into four
banks of eight registers selectable via SFR PSW
bits <4:3> (RS1/RS0; see Table 3), the next 16 bytes
above the register banks form a block of bit addressable
memory space.
The upper 128 bytes are not allocated for any special area
or functions.
Table 3
Bank selection
RS1
RS0
BANK
0
Bank 0
0
1
Bank 1
1
0
Bank 2
1
Bank 3
handbook, halfpage
MBK956
accessible
by indirect
addressing
only
DATA
MEMORY
FFH
upper 128 bytes
lower 128 bytes
80H
7FH
00H
SPECIAL
FUNCTION
REGISTERS
accessible
by direct
and indirect
addressing
accessible
by direct
addressing
only
Fig.6 Internal Data memory.
handbook, halfpage
GSA060
07H
00H
0FH
08H
17H
10H
1FH
18H
2FH
7FH
20H
bit-addressable
space
(bit addresses
00H to 7FH)
4 banks of
8 registers
(R0 to R7)
bank select
bits in PSW
11 = BANK 3
01 = BANK 1
00 = BANK 0
10 = BANK 2
Fig.7 Lower 128 bytes of internal RAM.
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