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參數(shù)資料
| 型號： | SAA5667HL/NNNN |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100 |
| 文件頁數(shù)： | 76/112頁 |
| 文件大?。?/td> | 537K |
| 代理商： | SAA5667HL/NNNN |
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2004 Sep 03
66
Philips Semiconductors
Product specication
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA56xx
23 DISPLAY
The display section (see Fig.25) is based on the
requirements for a Level 1.5 WST Teletext and US Closed
Caption. There are some enhancements for use with
locally generated on-screen displays.
The display section reads the contents of the Display
memory and interprets the control/character codes. From
this information and other global settings, the display
produces the required RGB signals and Video/Data (Fast
Blanking) signal for a TV signal processing device.
The display is synchronized to the TV signal processing
device by horizontal and vertical sync signals from
external circuits (Slave Sync mode). All display timings are
derived from these signals.
The SAA56xx display section incorporates a number of
enhancements over the rest of the SAA55xx family,
including 100 Hz (2H/2V only) operation, two page mode
(50/60 Hz only), increased DRCS/Special Graphics and a
larger Character ROM.
handbook, full pagewidth
MICROPROCESSOR
INTERFACE
DISPLAY
TIMING
HSYNC
VSYNC
CHARACTER
FONT
ADDRESSING
address
data
address
data
address
data
control
to memory interface
from memory interface
PHASE
SELECTOR
FUNCTION REGISTERS
FOR PAGE A AND PAGE B
PAGE B
PARALLEL/SERIAL
CONVERTER WITH
SMOOTHING AND FRINGING
ATTRIBUTE HANDLING
FOR PAGE A AND PAGE B
CLUT RAM
DISPLAY DATA ADDRESSING
FOR PAGE A AND PAGE B
GSA062
CLK
12/24 MHz display
CHARACTER
ROM
AND
DRCs
DATA
BUFFER
DAC
GB
FB
R
Fig.25 Display block diagram.
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