參數(shù)資料
型號： SAA5667HL/NNNN
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁數(shù)： 91/112頁
文件大?。?/td> 537K
代理商： SAA5667HL/NNNN
2004 Sep 03
8
Philips Semiconductors
Product specication
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA56xx
G
47
O
pixel rate output of the GREEN colour information
R
48
O
pixel rate output of the RED colour information
VDS
52
O
video/data switch push-pull output for dot rate fast blanking
HSYNC
53
I
Schmitt triggered input for a TTL-level version of the horizontal sync pulse;
the polarity of this pulse is programmable by register bit TXT1.H POLARITY.
VSYNC
55
I
Schmitt triggered input for a TTL-level version of the vertical sync pulse; the
polarity of this pulse is programmable by register bit TXT1.V POLARITY.
VSSP
12, 60
periphery ground
VDDC
63
+3.3 V core power supply
OSCGND
69
crystal oscillator ground
XTALIN
70
I
12 MHz crystal oscillator input
XTALOUT
71
O
12 MHz crystal oscillator output
RESET
72
I
If the reset input is LOW for at least 24 crystal oscillator periods while the
oscillator is running, the device is reset (internal pull-up).
RESET
73
I
If the reset input is HIGH for at least 24 crystal oscillator periods while the
oscillator is running, the device is reset. This pin should be connected to
VDDC via a capacitor if an active HIGH reset is required (internal pull-down).
VDDP
75
+3.3 V periphery power supply
P1.0/INT1
76
I/O
Port 1. 8-bit programmable bidirectional port with alternative functions.
P1.0/INT1 is external interrupt 1 which can be triggered on the rising and
falling edge of the pulse; P1.1/T0 is Timer/counter 0; P1.2/INT0 is external
interrupt 0; P1.3/T1 is Timer/counter 1; P1.6/SCL0 is the serial clock input
for the I2C-bus; P1.7/SDA0 is the serial data port for the I2C-bus; P1.4/SCL1
is the serial clock input for the I2C-bus; P1.5/SDA1 is the serial data port for
the I2C-bus.
P1.1/T0
78
I/O
P1.2/INT0
79
I/O
P1.3/T1
80
I/O
P1.6/SCL0
81
I/O
P1.7/SDA0
82
I/O
P1.4/SCL1
83
I/O
P1.5/SDA1
84
I/O
RD
9
O
read control signal to external data memory
WR
10
O
write control signal to external data memory
EA
14
I
Control signal used to select external (LOW) or internal (HIGH) program
memory (internal pull-up).
PSEN
19
O
enable signal for external program memory
ALE
20
O
external latch enable signal; active HIGH
AD0 to AD7
85 to 92
I/O
address lines A0 to A7 multiplexed with data lines D0 to D7.
A0 to A7
49, 40, 39,
38, 27, 26,
23, 15
O
address lines A0 to A7
A8 to A14
67 to 64,
37, 36, 8
O
address lines A8 to A14
A15_LN to A17_LN
7, 77, 3
O
address lines A15 to A17; note 1
MOVX_WR
68
O
MOVX Write for Hitex 80C51 emulation (internal MOVX Write instruction)
MOVX_RD
74
O
MOVX Read for Hitex 80C51 emulation (internal MOVX Read instruction)
SYMBOL
PIN
TYPE
DESCRIPTION
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