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參數(shù)資料
| 型號： | SAA5667HL/NNNN |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100 |
| 文件頁數(shù)： | 46/112頁 |
| 文件大小： | 537K |
| 代理商： | SAA5667HL/NNNN |
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2004 Sep 03
39
Philips Semiconductors
Product specication
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA56xx
There are three methods of exiting Power-down:
External interrupt. Since the clock is stopped, an
external interrupt needs to be set level sensitive prior to
entering Power-down. The interrupt is serviced and,
following the instruction RETI, the next instruction to be
executed will be the one after the instruction that put the
device into Power-down mode.
Interrupt generated by the SAD DC Compare circuit.
When SAA56xx is configured in this mode, detection of
a certain analog threshold at the input to the SAD may
be used to trigger wake-up of the device, i.e. TV Front
Panel Key-press. As above, the interrupt is serviced
and, following the instruction RETI, the next instruction
to be executed will be the one following the instruction
that put the device into Power-down.
External hardware reset. This reset defines all SFRs
and Display memory, but maintains all other RAM
values. Code execution commences with the Program
Counter set to ‘0000’.
11 I/O FACILITY
The SAA56xx devices have 32 I/O lines, each of which can
be individually addressed, or form four parallel 8-bit
addressable ports: Port 0, Port 1, Port 2 and Port 3.
I2C-bus ports (P1.4, P1.5, P1.6 and P1.7) can only be
configured as open-drain.
11.1
Port type
All individual ports can be programmed to function in one
of four modes, the mode is defined by two associated Port
Configuration Registers: PnCFGA and PnCFGB (where
n = port number 0, 1, 2 or 3). The modes available are
open-drain, quasi-bidirectional, high-impedance and
push-pull.
11.1.1
OPEN-DRAIN (TTL, 5 V TOLERANT)
The open-drain mode can be used for bidirectional
operation of a port and requires an external pull-up
resistor. The pull-up voltage has a maximum value of
5.5 V, to allow connection of the device into a 5 V
environment.
11.1.2
QUASI-BIDIRECTIONAL (CMOS, 3V3 TOLERANT)
The quasi-bidirectional mode is a combination of
open-drain and push-pull. It requires an external pull-up
resistor to VDDP (normally 3.3 V).
When a LOW-to-HIGH signal transition is output from the
device, the pad is put into push-pull mode for one clock
cycle (166 ns) after which the pad goes into open-drain
mode. This mode is used to speed up the edges of signal
transitions. This is the default mode of operation of the
pads after reset.
11.1.3
HIGH-IMPEDANCE (TTL, 5 V TOLERANT)
The high-impedance mode can be used for input only
operation of the port. When using this configuration, the
two output transistors are turned off.
11.1.4
PUSH-PULL (CMOS, 3V3 TOLERANT)
The push-pull mode can be used for output only. In this
mode, the signal is driven to either 0 V or VDDP, which is
nominally 3.3 V.
12 INTERRUPT SYSTEM
The device has 15 interrupt sources, each of which can be
enabled or disabled. When enabled, each interrupt can be
assigned one of two priority levels. There are five
interrupts that are common to the 80C51. Two of these are
external interrupts (EX0 and EX1); the other three are
timer interrupts (ET0, ET1 and ET2). In addition to the
conventional 80C51, two application specific interrupts are
incorporated internal to the device, with the following
functionality:
Closed Caption Data Ready interrupt (ECC). This
interrupt is generated when the device is configured in
Closed Caption Acquisition mode. The interrupt is
activated at the end of the currently selected Slice Line,
as defined in the CCLIN SFR.
Display Busy interrupt (EBUSY). An interrupt is
generated when the display enters either a Horizontal or
Vertical Blanking Period. i.e. indicates when the
microcontroller can update the Display RAM without
causing undesired effects on the screen. This interrupt
can be configured in one of two modes using the
Memory Mapped Register (MMR) Configuration
Register (address 87FFH, bit TXT/V).
– Text Display Busy: An interrupt is generated on each
active horizontal display line when the Horizontal
Blanking Period is entered.
– Vertical Display Busy: An interrupt is generated on
each vertical display field when the Vertical Blanking
Period is entered.
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