2004 Mar 16
124
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
18.1.1
I
2
C-
BUS FORMAT
Table 67
I
2
C-bus write access to control registers; see Table 72
Table 68
I
2
C-bus write access to cursor bit map (subaddress FEH); see Table 72
Table 69
I
2
C-bus write access to colour look-up table (subaddress FFH); see Table 72
Table 70
I
2
C-bus read access to control registers; see Table 72
Table 71
I
2
C-bus read access to cursor bit map or colour LUT; see Table 72
Table 72
Explanations of Tables 67 to 71
Notes
1.
2.
X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read.
If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed.
S 1 0 0 0 1 0 0 0 A SUBADDRESS
A
DATA 0
A
--------
DATA n
A
P
S 1 0 0 0 1 0 0 0 A FEH
A
RAM ADDRESS
A
DATA 0
A
--------
DATA n
A
P
S 1 0 0 0 1 0 0 0 A FFH
A
RAM ADDRESS
A
DATA 0R
A
DATA 0G
A
DATA 0B
A
--------
P
S 1 0 0 0 1 0 0 0 A SUBADDRESS
A
Sr
1 0 0 0 1 0 0 1
A
DATA 0
Am
--------
DATA n
Am
P
S 1 0 0 0 1 0 0 0 A FEH
or
FFH
A RAM ADDRESS A Sr 1 0 0 0 1 0 0 1 A DATA 0 Am -------- DATA n Am P
CODE
DESCRIPTION
S
Sr
1 0 0 0 1 0 0 X; note 1
A
Am
SUBADDRESS; note 2
DATA
--------
P
RAM ADDRESS
START condition
repeated START condition
slave address
acknowledge generated by the slave
acknowledge generated by the master
subaddress byte
data byte
continued data bytes and acknowledges
STOP condition
start address for RAM access