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參數(shù)資料
| 型號(hào)： | SAA7108 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | Codec |
| 英文描述： | PC-CODEC |
| 中文描述： | PC的編解碼器 |
| 文件頁(yè)數(shù)： | 19/202頁(yè) |
| 文件大小： | 983K |
| 代理商： | SAA7108 |
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2004 Mar 16
19
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
8.1
Reset conditions
To activate the reset a pulse at least of 2 crystal clocks
duration is required.
During reset (RESET = LOW) plus an extra 32 crystal
clock periods, FSVGC, VSVGC, CBO, HSVGC and
TTX_SRES are set to input mode and HSM_CSYNC and
VSM are set to 3-state. A reset also forces the I
2
C-bus
interface to abort any running bus transfer and sets it into
receive condition.
After reset, the state of the I/Os and other functions is
defined by the strapping pins until an I
2
C-bus access
redefines the corresponding registers; see Table 2.
Table 2
Strapping pins
8.2
Input formatter
The input formatter converts all accepted PD input data
formats, either RGB or Y-C
B
-C
R
, to a common internal
RGB or Y-C
B
-C
R
data stream.
When double-edge clocking is used, the data is internally
split into portions PPD1 and PPD2. The clock edge
assignment must be set according to the I
2
C-bus control
bits EDGE1 and EDGE2 for correct operation.
If Y-C
B
-C
R
is being applied as a 27 Mbyte/s data stream,
the output of the input formatter can be used directly to
feed the video encoder block.
8.3
RGB LUT
The three 256-byte RAMs of this block can be addressed
by three 8-bit wide signals, thus it can be used to build any
transformation, e.g. a gamma correction for RGB signals.
In the event that the indexed colour data is applied, the
RAMs are addressed in parallel.
The LUTs can either be loaded by an I
2
C-bus write access
or can be part of the pixel data input through the PD port.
Inthelattercase,256
×
3bytesfortheR, Gand B LUTare
expected at the beginning of the input video line, two lines
before the line that has been defined as first active line,
until the middle of the line immediately preceding the first
active line. The first 3 bytes represent the first RGB LUT
data, and so on.
8.4
Cursor insertion
A 32
×
32 dots cursor can be overlaid as an option; the bit
map of the cursor can be uploaded by an I
2
C-bus write
access to specific registers or in the pixel data input via the
PDport.Inthelattercasethe256 bytesdefiningthecursor
bit map (2 bits per pixel) are expected immediately
following the last RGB LUT data in the line preceding the
first active line.
The cursor bit map is set up as follows: each pixel
occupies 2 bits. The meaning of these bits depends on the
CMODE I
2
C-bus register as described in Table 5.
Transparent means that the input pixels are passed
through, the ‘cursor colours’ can be programmed in
separate registers.
The bit map is stored with 4 pixels per byte, aligned to the
least significant bit. So the first pixel is in bits 0 and 1, the
next pixel in bits 3 and 4 and so on. The first index is the
column, followed by the row; index 0,0 is the upper left
corner.
Table 3
Layout of a byte in the cursor bit map
For each direction, there are 2 registers controlling the
position of the cursor, one controls the position of the
‘hot spot’, the other register controls the insertion position.
The hot spot is the ‘tip’ of the pointer arrow.
PIN
TIED
PRESET
FSVGC (pin G1)
LOW
NTSC M encoding, PIXCLK
fits to 640
×
480 graphics
input
HIGH PAL B/G encoding, PIXCLK
fits to 640
×
480 graphics
input
LOW
4 : 2 : 2 Y-C
B
-C
R
graphics
input (format 0)
HIGH 4 : 4 : 4 RGB graphics input
(format 3)
LOW
input demultiplex phase:
LSB = LOW
HIGH input demultiplex phase:
LSB = HIGH
LOW
input demultiplex phase:
MSB = LOW
HIGH input demultiplex phase:
MSB = HIGH
LOW
slave (FSVGC, VSVGC and
HSVGC are inputs, internal
colour bar is active)
HIGH master (FSVGC, VSVGC
and HSVGC are outputs)
VSVGC (pin F1)
CBO (pin G3)
HSVGC (pin E3)
TTXRQ_XCLKO2
(pin C4)
D7
D6
D5
D4
D3
D2
D1
D0
pixel n + 3
D1
pixel n + 2
D1
pixel n + 1
D1
pixel n
D1
D0
D0
D0
D0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7109 | PC-CODEC |
| SAA7108E | PC-CODEC |
| SAA7109E | PC-CODEC |
| SAA7108AE | HD-CODEC |
| SAA7109A | HD-CODEC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7108AE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC |
| SAA7108E | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PC-CODEC |
| SAA7109 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PC-CODEC |
| SAA7109A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC |
| SAA7109AE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC |
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