
2004 Mar 16
163
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
18.2.2.20 Subaddress 13H
Table 169
RT/X port output control; 13H[7:0]
BIT
DESCRIPTION
SYMBOL
VALUE
FUNCTION
7
RTCO output enable
RTCE
0
1
0
1
3-state
enabled
HREF (see Fig.31)
HS:
programmablewidthinLLC8stepsviaHSB[7:0]06H[7:0]
and HSS[7:0] 07H[7:0]
fine position adjustment in LLC2 steps via HDEL[1:0]
11H[5:4] (see Fig.31)
V123; see Figs 29 and 30
ITU 656 related field ID; see Figs 29 and 30
inverted V123
inverted ITU 656 related field ID
copy of inverted HLCK status bit (default)
fast horizontal lock indicator (for special applications only)
ITU 656
ITU 656 like format with modified field blanking according
to VGATE position (programmable via VSTA[8:0] 17H[0]
15H[7:0], VSTO[8:0] 17H[1] 16H[7:0] and VGPS[17H[2]])
Y-C
B
-C
R
4 : 2 : 2 8-bit format (no SAV/EAV codes inserted)
reserved
multiplexed AD2/AD1 bypass (bits 8 to 1) dependent on
mode settings; if both ADCs are selected AD2 is output at
CREF = 1 and AD1 is output at CREF = 0
multiplexed AD2/AD1 bypass (bits 7 to 0) dependent on
mode settings; if both ADCs are selected AD2 is output at
CREF = 1 and AD1 is output at CREF = 0
reserved
multiplexed ADC MSB/LSB bypass dependent on mode
settings; only one ADC should be selected at a time;
ADx8 to ADx1 are outputs at CREF = 1 and ADx7 to ADx0
are outputs at CREF = 0
6
X port XRH output
selection
XRHS
5 and 4 X port XRV output
selection
XRVS[1:0]
00
01
10
11
0
1
000
001
3
horizontal lock indicator
selection
HLSEL
2 to 0
XPD7 to XPD0 (port
output format selection);
see Section 10.4
OFTS[2:0]
010
011
100
101
110
111