2
8
P
P
P
S
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FIR-PREFILTER
PRESCALER
AND
SCALER BCS
GENERAL PURPOSE
VBI DATA SLICER
VIDEO/TEXT
ARBITER
TEXT
FIFO
VIDEO
FIFO
PROGRAMMING
REGISTER
ARRAY
A/B
REGISTER
MUX
EVENT CONTROLLER
I
X PORT I/O FORMATTING
EXPANSION PORT PIN MAPPING
I/O CONTROL
I
2
C-BUS
REAL-TIME OUTPUT
LLC
P8
AI2D
LINE
FIFO
BUFFER
VERTICAL
SCALING
HORIZONTAL
FINE
(PHASE)
SCALING
32
to
8(16)
MUX
G14
ITRI
N10
AGND
P12
AI1D
M10
AOUT
P6
AI24
P7
AI23
P9
AI22
P10
AI21
P11
AI12
P13
AI11
P3
XTALOd
P2
XTALId
P4
XTOUTd
N14
CE
M12
M14
N4
TCKd
M6
TMSd
M5
TDId
N6
VDDXd
L8
VSSXd
P5
VDDId
D11, F11,
J4, J11,
L4, L11
VDDEd
D10, G11,
L7, L9
VDDAd
M8, M9,
N11
VSSId
E11, K4,
K11
VSSEd
H4, H11,
L6, M13
VSSAd
M7,
N7 to N9,
N12, N13
AMXCLK
J12
TDOd
N5
AMCLK
K12
ALRCLK
(1)
J13
ASCLK
K14
LLC2
L14
RTCO
L13
RTS0
K13
RTS1
L10
XCLK
M3
XDQ
M4
K2, K3,
L1 to L3
M1, M2, N1
XRH
N2
XRV
L5
XRDY
N3
SDAd
L12
SCLd
M11
TEST5
J2
TEST4
J1
TEST3
J3
TEST2
C10
TEST1
B10
TEST0
H13
A13, D12, C12,
B12, A12, C11,
B11, A11
XTRI
K1
chrominance of 16-bit input
BOUNDARY
SCAN
TEST
CLOCK GENERATION
AND
POWER-ON CONTROL
ANALOG
DUAL
ADC
DIGITAL
DECODER
WITH
ADAPTIVE
COMB
FILTER
AUDIO
CLOCK
GENERATION
J14
ITRDY
H12
ICLK
G13
IGP1
F14
IGP0
F13
IGPV
G12
IGPH
H14
IDQ
E14, D14,
C14, B14,
E13, D13,
C13, B13
IPD[7:0]
HPD[7:0]
XPD[7:0]
RES
SAA7108E
SAA7109E
TRSTd
(1)
MHB887
Fig.3 Block diagram (video decoder part).
(1) The pins RTCO and ALRCLK are used for configuration of the I
2
C-bus interface
and the definition of the crystal oscillator frequency at RESET (pin strapping).