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參數(shù)資料
| 型號： | SAA7108 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | Codec |
| 英文描述： | PC-CODEC |
| 中文描述： | PC的編解碼器 |
| 文件頁數(shù)： | 22/202頁 |
| 文件大小： | 983K |
| 代理商： | SAA7108 |
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2004 Mar 16
22
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
Phase variant interpolation is achieved on this bitstream in
the internal teletext encoder, providing sufficient small
phase jitter on the output text lines.
TTXRQ_XCLKO2 provides a fully programmable request
signal to the teletext source, indicating the insertion period
of bitstream at lines which can be selected independently
for both fields. The internal insertion window for text is set
to 360 (PAL WST), 296 (NTSC WST) or 288 (NABTS)
teletext bits including clock run-in bits. The protocol and
timing are illustrated in Fig.50.
Alternatively, this pin can be provided with a buffered
crystal clock (XCLK) of 13.5 MHz.
8.12.3
V
IDEO
P
ROGRAMMING
S
YSTEM
(VPS)
ENCODING
Five bytes of VPS information can be loaded via the
I
2
C-bus and will be encoded in the appropriate format into
line 16.
8.12.4
C
LOSED
C
APTION ENCODER
Using this circuit, data in accordance with the specification
of Closed Caption or extended data service, delivered by
the control interface, can be encoded (line 21). Two
dedicated pairs of bytes (two bytes per field), each pair
preceded by run-in clocks and framing code, are possible.
The actual line number in which data is to be encoded, can
be modified in a certain range.
The data clock frequency is in accordance with the
definition for NTSC M standard 32 times horizontal line
frequency.
DataLOWattheoutputoftheDACscorrespondsto0 IRE,
data HIGH at the output of the DACs corresponds to
approximately 50 IRE.
It is also possible to encode Closed Caption data for 50 Hz
field frequencies at 32 times the horizontal line frequency.
8.12.5
A
NTI
-
TAPING
(SAA7108E
ONLY
)
For more information contact your nearest Philips
Semiconductors sales office.
8.13
RGB processor
This block contains a dematrix in order to produce RED,
GREEN and BLUE signals to be fed to a SCART plug.
Before Y, C
B
and C
R
signals are de-matrixed, individual
gain adjustment for Y and colour difference signals and
2 times oversampling for luminance and 4 times
oversampling for colour difference signals is performed.
The transfer curves of luminance and colour difference
components of RGB are illustrated in Figs 9 and 10.
8.14
Triple DAC
Both Y and C signals are converted from digital-to-analog
in a 10-bit resolution at the output of the video encoder.
Y and C signals are also combined into a 10-bit CVBS
signal.
The CVBS output signal occurs with the same processing
delay as the Y, C and optional RGB or C
R
-Y-C
B
outputs.
Absolute amplitude at the input of the DAC for CVBS is
reduced by
15
16
with respect to Y and C DACs to make
maximum use of the conversion ranges.
RED, GREEN and BLUE signals are also converted from
digital-to-analog, each providing a 10-bit resolution.
The reference currents of all three DACs can be adjusted
individually in order to adapt for different output signals.
In addition, all reference currents can be adjusted
commonly to compensate for small tolerances of the
on-chip band gap reference voltage.
Alternatively, all currents can be switched off to reduce
power dissipation.
All three outputs can be used to sense for an external load
(usually 75
) during a pre-defined output. A flag in the
I
2
C-bus status byte reflects whether a load is applied or
not.
If the SAA7108E; SAA7109E is required to drive a second
(auxiliary) VGA monitor, the DACs receive the signal
directly from the cursor insertion block. In this event, the
DACs are clocked at the incoming PIXCLKI instead of the
27 MHz crystal clock used in the video encoder.
8.15
Timing generator
The synchronization of the SAA7108E; SAA7109E is able
to operate in two modes; slave mode and master mode.
In slave mode, the circuit accepts sync pulses on the
bidirectional FSVGC (frame sync), VSVGC (vertical sync)
and HSVGC (horizontal sync) pins: the polarities of the
signals can be programmed. The frame sync signal is only
necessary when the input signal is interlaced, in other
casesitmaybeomitted.Iftheframesyncsignalispresent,
it is possible to derive the vertical and the horizontal phase
from it by setting the HFS and VFS bits. HSVGC and
VSVGC are not necessary in this case, so it is possible to
switch the pins to output mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7109 | PC-CODEC |
| SAA7108E | PC-CODEC |
| SAA7109E | PC-CODEC |
| SAA7108AE | HD-CODEC |
| SAA7109A | HD-CODEC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7108AE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC |
| SAA7108E | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PC-CODEC |
| SAA7109 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PC-CODEC |
| SAA7109A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC |
| SAA7109AE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC |
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