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參數(shù)資料
| 型號： | SAA7108 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | Codec |
| 英文描述： | PC-CODEC |
| 中文描述： | PC的編解碼器 |
| 文件頁數(shù)： | 15/202頁 |
| 文件大?。?/td> | 983K |
| 代理商： | SAA7108 |
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2004 Mar 16
15
Philips Semiconductors
Product specification
PC-CODEC
SAA7108E; SAA7109E
8
FUNCTIONAL DESCRIPTION OF DIGITAL VIDEO
ENCODER PART
The digital video encoder encodes digital luminance and
colour difference signals (C
B
-Y-C
R
) or digital RGB signals
into analog CVBS, S-video and, optionally, RGB or
C
R
-Y-C
B
signals. NTSC M, PAL B/G and sub-standards
are supported.
The SAA7108E; SAA7109E can be directly connected to a
PC video graphics controller with a maximum resolution of
800
×
600 at a 50 or 60 Hz frame rate. A programmable
scaler scales the computer graphics picture so that it will fit
into a standard TV screen with an adjustable underscan
area. Non-interlaced-to-interlaced conversion is optimized
with an adjustable anti-flicker filter for a flicker-free display
at a very high sharpness.
Besides the most common 16-bit 4 : 2 : 2 C
B
-Y-C
R
input
format (using 8 pins with double edge clocking), other
C
B
-Y-C
R
and RGB formats are also supported; see
Tables 25 to 31.
Acomplete3
×
256bytesLook-UpTable(LUT),whichcan
be used, for example, as a separate gamma corrector, is
located in the RGB domain; it can be loaded either through
the video input port PD (Pixel Data) or via the I
2
C-bus.
The SAA7108E; SAA7109E supports a 32
×
32
×
2-bit
hardware cursor, the pattern of which can also be loaded
through the video input port or via the I
2
C-bus.
It is also possible to encode interlaced 4 : 2 : 2 video
signals such as PC-DVD; for that the anti-flicker filter, and
in most cases the scaler, will simply be bypassed.
Besides the applications for video output, the SAA7108E;
SAA7109E can also be used for generating a kind of
auxiliary VGA output, when the RGB non-interlaced input
signal is fed to the DACs. This may be of interest for
example, when the graphics controller provides a second
graphics window at its video output port.
The basic encoder function consists of subcarrier
generation, colour modulation and insertion of
synchronization signals at a crystal-stable clock rate of
13.5 MHz (independent of the actual pixel clock used at
the input side), corresponding to an internal 4 : 2 : 2
bandwidth in the luminance/colour difference domain.
Luminance and chrominance signals are filtered in
accordance with the standard requirements of “RS-170-A”
and “ITU-R BT.470-3”
For ease of analog post filtering the signals are twice
oversampled to 27 MHz before digital-to-analog
conversion.
The total filter transfer characteristics (scaler and
anti-flicker filter are not taken into account) are illustrated
in Figs 5 to 10. All three DACs are realized with full 10-bit
resolution. The C
R
-Y-C
B
to RGB dematrix can be
bypassed (optionally) in order to provide the upsampled
C
R
-Y-C
B
input signals.
The8-bitmultiplexedC
B
-Y-C
R
formatsare“ITU-R BT.656”
(D1 format) compatible, but the SAV and EAV codes can
be decoded optionally, when the device is operated in
slave mode. For assignment of the input data to the rising
or falling clock edge see Tables 25 to 31.
In order to display interlaced RGB signals through a
euro-connector TV set, a separate digital composite sync
signal (pin HSM_CSYNC) can be generated; it can be
advanced up to 31 periods of the 27 MHz crystal clock in
order to be adapted to the RGB processing of a TV set.
The SAA7108E; SAA7109E synthesizes all necessary
internal signals, colour subcarrier frequency and
synchronization signals from that clock.
Wide screen signalling data can be loaded via the I
2
C-bus
and is inserted into line 23 for standards using a 50 Hz
field rate.
VPS data for program dependent automatic start and stop
of such featured VCRs is loadable via the I
2
C-bus.
The IC also contains Closed Caption and extended data
servicesencoding(line 21),andsupportsteletextinsertion
fortheappropriatebitstreamformatata27 MHzclockrate
(see Fig.50). It is also possible to load data for the copy
generation management system into line 20 of every field
(525/60 line counting).
A number of possibilities are provided for setting different
video parameters such as:
Black and blanking level control
Colour subcarrier frequency
Variable burst amplitude etc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7109 | PC-CODEC |
| SAA7108E | PC-CODEC |
| SAA7109E | PC-CODEC |
| SAA7108AE | HD-CODEC |
| SAA7109A | HD-CODEC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7108AE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC |
| SAA7108E | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PC-CODEC |
| SAA7109 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PC-CODEC |
| SAA7109A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC |
| SAA7109AE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:HD-CODEC |
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