參數(shù)資料
型號： SC16C852SVIET
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 1.8 V dual UART, 20 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface
中文描述： 2 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PBGA36
封裝： 3.50 X 3.50 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, PLASTIC, SOT-912-1, TFBGA-36
文件頁數(shù)： 23/48頁
文件大小： 221K
代理商： SC16C852SVIET
SC16C852SV_1
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 23 September 2008
23 of 48
NXP Semiconductors
SC16C852SV
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs and set the receive FIFO trigger
levels.
7.3.1
FIFO mode
[1]
For 128-byte FIFO mode, refer to
Section 7.16
,
Section 7.17
,
Section 7.18
.
[2]
For 128-byte FIFO mode, refer to
Section 7.15
,
Section 7.17
,
Section 7.18
.
Table 9.
Bit
7:6
FIFO Control Register bits description
Symbol
Description
FCR[7:6]
Receive trigger level in 32-byte FIFO mode.
[1]
These bits are used to set the trigger level for receive FIFO interrupt and flow
control. The SC16C852SV will issue a receive ready interrupt when the
number of characters in the receive FIFO reaches the selected trigger level.
Refer to
Table 10
.
FCR[5:4]
Transmit trigger level in 32-byte FIFO mode.
[2]
These bits are used to set the trigger level for the transmit FIFO interrupt and
flow control. The SC16C852SV will issue a transmit empty interrupt when the
number of characters in FIFO drops below the selected trigger level. Refer to
Table 11
.
FCR[3]
reserved
FCR[2]
XMIT FIFO reset.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
FCR[1]
RCVR FIFO reset.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
FCR[0]
FIFO enable.
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO
5:4
3
2
1
0
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相關代理商/技術參數(shù)
參數(shù)描述
SC16C852SVIET,115 功能描述:UART 接口集成電路 UART 2-CH 128Byte FIFO 1.8V 36-Pin RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16C852SVIET,151 功能描述:UART 接口集成電路 UART 2-CH 128Byte FIFO 1.8V 36-Pin RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16C852SVIET,157 功能描述:UART 接口集成電路 UART 2-CH 128Byte FIFO 1.8V 36-Pin RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16C852V 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
SC16C852V_08 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V dual UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface
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