參數(shù)資料
型號: SI3230PPQX-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 108/108頁
文件大?。?/td> 0K
描述: BOARD EVAL W/DISCRETE INTERFACE
標準包裝: 1
系列: ProSLIC®
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: Si3230
已供物品: 板,CD
Si3230
Preliminary Rev. 0.96
99
Not
Recommended
fo
r N
ew
D
esi
gn
s
5. Pin Descriptions: Si3230
Pin #
QFN
Pin #
TSSOP
Name
Description
35
1
CS
Chip Select.
Active low. When inactive, SCLK and SDI are ignored and SDO is high imped-
ance. When active, the serial port is operational.
36
2
INT
Interrupt.
Maskable interrupt output. Open drain output for wire-ORed operation.
37
3
PCLK
PCM Bus Clock.
Clock input.
38
4
TEST2
Test.
Enables test modes for Silicon Labs internal testing. This pin should always be
tied to ground for normal operation.
15
NC
No Connect.
2
6
FSYNC
Frame Synch.
8 kHz frame synchronization signal for the PCM bus. May be short or long pulse
format.
3
7
RESET
Reset.
Active low input. Hardware reset used to place all control registers in the default
state.
4
8
SDCH
DC Monitor.
DC-DC converter monitor input used to detect overcurrent situations in the con-
verter.
27
28
29
30
31
34 33 32
1
2
3
4
5
6
7
8
9
10
11
12 13
26
25
14
35
36
37
38
15 16 17 18 19
24
23
22
21
20
NC
FSYNC
RESET
SDCH
SDCL
VDDA1
IREF
CAPP
QGND
CAPM
STIPDC
SRINGDC
STIPE
SV
BAT
SR
IN
G
E
ST
IPA
C
SRI
N
G
A
C
IGM
N
G
NDA
IGMP
IRINGN
IRINGP
VDDA2
ITIPP
ITIPN
VDDD
GNDD
TEST2
DCFF
DCDRV
SDITHRU
SD
O
SD
I
SCL
K
CS
IN
T
PCL
K
TEST1
QFN
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
STIPAC
SRINGAC
IGMN
GNDA
IGMP
IRINGN
IRINGP
VDDA2
ITIPP
ITIPN
VDDD
GNDD
DCFF
DCDRV
SDITHRU
SDO
SDI
SCLK
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CS
INT
PCLK
TEST2
NC
FSYNC
RESET
SDCH
SDCL
VDDA1
IREF
CAPP
QGND
CAPM
STIPDC
SRINGDC
STIPE
SVBAT
SRINGE
TEST1
TSSOP
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