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| 型號： | SI3230PPQX-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 31/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL W/DISCRETE INTERFACE |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ProSLIC® |
| 主要目的： | 接口，模擬前端（AFE） |
| 已用 IC / 零件： | Si3230 |
| 已供物品： | 板，CD |
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Si3230
Preliminary Rev. 0.96
29
Not
Recommended
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2.3.4. Enhanced FSK Waveform Generation
Silicon revisions C and higher support enhanced FSK
generation capabilities, which can be enabled by setting
FSKEN = 1 (direct Register 108, bit 6) and REN = 1
(direct Register 32, bit 6). In this mode, the user can
define mark (1) and space (0) attributes once during
initialization by defining indirect registers 99–104. The
user need only indicate 0-to-1 and 1-to-0 transitions in
the information stream. By writing to FSKDAT (direct
Register 52), this mode applies a 24 kHz sample rate to
tone generator 1 to give additional resolution to timers
and frequency generation. Application Note 32 gives
detailed instructions on how to implement FSK in this
mode. Additionally, sample source code is available
from Silicon Laboratories upon request.
2.3.5. Tone Generator Interrupts
Both the active and inactive timers can generate their
own interrupt to signal “on/off” transitions to the
software. The timer interrupts for tone generator 1 can
be individually enabled by setting the O1AE and O1IE
bits (direct Register 21, bits 0 and 1, respectively).
Timer interrupts for tone generator two are O2AE and
O2IE (direct Register 21, bits 2 and 3, respectively). A
pending interrupt for each of the timers is determined by
reading the O1AP, O1IP, O2AP, and O2IP bits in the
Interrupt Status 1 register (direct Register 18, bits 0
through 3, respectively).
2.4. Ringing Generation
The ProSLIC provides fully programmable internal
balanced ringing with or without a dc offset to ring a
wide variety of terminal devices. All parameters
associated with ringing are software programmable:
ringing frequency, waveform, amplitude, dc offset, and
ringing cadence. Both sinusoidal and trapezoidal ringing
waveforms are supported, and the trapezoidal crest
factor is programmable. Ringing signals of up to 88 V
peak or more can be generated, enabling the ProSLIC
to drive a 5 REN (1380
+ 40 F) ringer load across
loop lengths of 2000 feet (160
) or more.
2.4.1. Ringing Architecture
The ringing generator architecture is nearly identical to
that of the tone generator. The sinusoid ringing
waveform is generated using an internal two-pole
resonance
oscillator
circuit
with
programmable
frequency and amplitude. However, since ringing
frequencies are very low compared to the audio band
signaling
frequencies,
the
ringing
waveform
is
generated at a 1 kHz rate instead of 8 kHz.
The ringing generator has two timers that function the
same as for the tone generator timers. They allow on/off
cadence settings up to 8 seconds on/ 8 seconds off. In
addition to controlling ringing cadence, these timers
control the transition into and out of the ringing state.
Table 26 summarizes the list of registers used for
ringing generation.
Note:
Tone generator 2 should not be enabled concurrently
with the ringing generator due to resource sharing
within the hardware.
Table 26. Registers for Ringing Generation
Parameter
Range/ Description
Register
Bits
Location
Ringing Waveform
Sine/Trapezoid
TSWS
Direct Register 34
Ringing Voltage Offset Enable
Enabled/
Disabled
RVO
Direct Register 34
Ringing Active Timer Enable
Enabled/
Disabled
RTAE
Direct Register 34
Ringing Inactive Timer Enable
Enabled/
Disabled
RTIE
Direct Register 34
Ringing Oscillator Enable
Enabled/
Disabled
ROE
Direct Register 34
Ringing Oscillator Active Timer
0 to 8 seconds
RAT[15:0]
Direct Registers 48 and 49
Ringing Oscillator Inactive Timer
0 to 8 seconds
RIT[15:0]
Direct Registers 50 and 51
Linefeed Control (Initiates Ringing State)
Ringing State = 100b
LF[2:0]
Direct Register 64
High Battery Voltage
0 to –94.5 V
VBATH[5:0]
Direct Register 74
Ringing dc voltage offset
0 to 94.5 V
ROFF[15:0]
Indirect Register 19
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