參數(shù)資料
型號: SI3230PPQX-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 74/108頁
文件大小: 0K
描述: BOARD EVAL W/DISCRETE INTERFACE
標準包裝: 1
系列: ProSLIC®
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: Si3230
已供物品: 板,CD
Si3230
68
Preliminary Rev. 0.96
Not
Recommended
fo
r N
ew
D
esi
gn
s
Reset settings = 0000_0000
Reset settings = 0011_0010 (revision C); 0101_0100 (subsequent revisions)
Register 51. Ringing Oscillator Inactive Timer—High Byte
Bit
D7D6D5D4D3D2
D1
D0
Name
RIT[15:8]
Type
R/W
Bit
Name
Function
7:0
RIT[15:8]
Ringing Inactive Timer.
Register 52. FSK Data
Bit
D7D6D5D4D3D2
D1
D0
Name
FSKDAT
Type
R/W
Bit
Name
Function
7:1
Reserved
Read returns zero.
0
FSKDAT
FSK Data.
When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6), this
bit serves as the buffered input for FSK generation bit stream data.
Register 63. Loop Closure Debounce Interval
Bit
D7D6D5D4D3D2
D1
D0
Name
LCD[7:0]
Type
Bit
Name
Function
7:0
LCD[7:0]
Loop Closure Debounce Interval for Automatic Ringing.
This register sets the loop closure debounce interval for the ringing silent period when
using automatic ringing cadences. The value may be set between 0 ms (0x00) and
159 ms (0x7F) in 1.25 ms steps.
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