參數(shù)資料
型號(hào): SI3230PPQX-EVB
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 42/108頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL W/DISCRETE INTERFACE
標(biāo)準(zhǔn)包裝: 1
系列: ProSLIC®
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: Si3230
已供物品: 板,CD
Si3230
Preliminary Rev. 0.96
39
Not
Recommended
fo
r N
ew
D
esi
gn
s
Figure 19. SPI Daisy Chain Mode
CPU
SDO
CS
SDI
CS
SD I
SD ITHR U
SD O
CS
SD I
SD ITHR U
SD O
C7 C6 C5 C4 C3 C2 C1 C0
R/W
A6 A5 A4 A3 A2 A1 A0
– C7 C6 C5 C4 C3 C2 C1
C7 C6 C5 C4 C3 C2
Chip Select Byte
Address Byte
Data Byte
SCLK
SD I0
SD I1
SD I2
SD I3
R/W
A6 A5 A4 A3 A2 A1 A0
R/W
A6 A5 A4 A3 A2 A1 A0
R/W
A6 A5 A4 A3 A2 A1 A0
C7 C6 C5 C4 C3
Note: D uring chip select byte, SDITHRU = SDI delayed by one SCLK. Each device daisy-chained looks at the
LSB of the chip select byte for its chip select.
CS
SDI
SDITHRU
SDO
CS
SDI
SDITHRU
SDO
SDI0
SDI3
SDI2
SDI1
D7 D6 D5 D4 D3 D2 D1 D0
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