參數(shù)資料
型號(hào)： SI3230PPQX-EVB
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 39/108頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL W/DISCRETE INTERFACE
標(biāo)準(zhǔn)包裝： 1
系列： ProSLIC®
主要目的： 接口，模擬前端（AFE）
已用 IC / 零件： Si3230
已供物品： 板，CD
Si3230
36
Preliminary Rev. 0.96
Not
Recommended
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ew
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2.7. Two-Wire Impedance Matching
The ProSLIC provides on-chip programmable two-wire
impedance settings to meet a wide variety of worldwide
two-wire
return
loss
requirements.
The
two-wire
impedance is programmed by loading one of the eight
available impedance values into the TISS[2:0] bits of the
Two-Wire Impedance Synthesis Control register (direct
Register 10). If direct Register 10 is not user-defined,
the default setting of 600
will be loaded into the TISS
register.
Real and complex two-wire impedances are realized by
internal feedback of a programmable amplifier (RAC) a
switched
capacitor
network
(XAC)
and
a
transconductance amplifier (Gm). (See Figure 16.) RAC
creates the real portion and XAC creates the imaginary
portion of Gm’s input. Gm then creates a current that
models the desired impedance value to the subscriber
loop. The differential ac current is fed to the subscriber
loop via the ITIPP and IRINGP pins through an off-chip
current buffer (IBUF), which is implemented using
transistor Q1 and Q2 (see Figure on page 15). Gm is
referenced to an off-chip resistor (R15).
The ProSLIC also provides a means to compensate for
degraded
subscriber
loop
conditions
involving
excessive line capacitance (leakage). The CLC[1:0] bits
of direct Register 10 increase the ac signal magnitude
to compensate for the additional loss at the high end of
the audio frequency range. The default setting of
CLC[2:0] assumes no line capacitance.
Silicon revisions C and higher support the option to
remove
the
internal
reference
resistor
used
to
synthesize ac impedances for 600 + 2.16
F and
900 + 2.16
F settings so that an external resistor
reference may be used. This option is enabled by
setting ZSEXT = 1 (direct Register 108, bit 4).
2.8. Clock Generation
The ProSLIC will generate the necessary internal clock
frequencies from the PCLK input. PCLK must be
synchronous to the 8 kHz FSYNC clock and run at one
of the following rates: 256kHz, 512kHz, 768kHz,
1.024 MHz, 1.536 MHz, 2.048 MHz, 4.096 MHz or
8.192 MHz. The ratio of the PCLK rate to the FSYNC
rate is determined via a counter clocked by PCLK. The
three-bit ratio information is automatically transferred
into an internal register, PLL_MULT, following a reset of
the ProSLIC. The PLL_MULT is used to control the
internal PLL which multiplies PCLK as needed to
generate 16.384 MHz rate needed to run the internal
filters and other circuitry.
The PLL clock synthesizer settles very quickly following
power up. However, the settling time depends on the
PCLK frequency and it can be approximately predicted
by the following equation:
2.9. Interrupt Logic
The ProSLIC is capable of generating interrupts for the
following events:
Loop current/ring ground detected
Ring trip detected
Power alarm
DTMF digit detected (Si3230 and Si3211 only)
Active timer 1 expired
Inactive timer 1 expired
Active timer 2 expired
Inactive timer 2 expired
Ringing active timer expired
Ringing inactive timer expired
Pulse metering active timer expired
Pulse metering inactive timer expired
Indirect register access complete
The interface to the interrupt logic consists of six
registers. Three interrupt status registers contain 1 bit
for each of the above interrupt functions. These bits will
be set when an interrupt is pending for the associated
resource. Three interrupt enable registers also contain 1
bit for each interrupt function. In the case of the interrupt
enable registers, the bits are active high. Refer to the
appropriate
functional
description
section
for
operational details of the interrupt functions.
When a resource reaches an interrupt condition, it will
signal an interrupt to the interrupt control block. The
interrupt control block will then set the associated bit in
the interrupt status register if the enable bit for that
interrupt is set. The INT pin is a NOR of the bits of the
interrupt status registers. Therefore, if a bit in the
interrupt status registers is asserted, IRQ will assert low.
Upon receiving the interrupt, the interrupt handler
should read interrupt status registers to determine
which resource is requesting service. To clear a pending
interrupt, write the desired bit in the appropriate
interrupt status register to 1. Writing a 0 has no effect.
This provides a mechanism for clearing individual bits
when multiple interrupts occur simultaneously. While the
interrupt status registers are non-zero, the INT pin will
remain asserted.
T
SETTLE
64
F
PCLK
-----------------
=
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