- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16215 > SI3232DC0-EVB (Silicon Laboratories Inc)DAUGHTER CARD W/SI3200 INTERFACE PDF資料下載
參數(shù)資料
| 型號(hào)： | SI3232DC0-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 47/128頁 |
| 文件大?。?/td> | 0K |
| 描述： | DAUGHTER CARD W/SI3200 INTERFACE |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ProSLIC® |
| 主要目的： | 接口，模擬前端（AFE） |
| 已用 IC / 零件： | Si3232 |
| 已供物品： | 板，CD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁當(dāng)前第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁
Si3232
Preliminary Rev. 0.96
25
Not
Recommended
fo
r N
ew
D
esi
gn
s
4.4. Linefeed Calibration
An internal calibration algorithm corrects for internal and
external component errors. The calibration is initiated by
setting the CAL register bit. Upon completion of the
calibration cycle, this bit is automatically reset.
It is recommended that a calibration be executed
following system powerup. Upon release of the chip
reset, the device is in the Open state, and calibration
can be initiated. Only one calibration should be
necessary as long as the system remains powered up.
The Dual ProSLIC calibration sequence consists of
SLIC mode calibration, monitor ADC calibration, and
audio path calibration. The calibration bits that are set in
registers CALR1 and CALR2 are executed in order of
MSB to LSB for each sequential register. CALR1, bit 7
starts the calibration sequence. CALR2 calibration bits
should be set before the CALR1 is written. The reserved
bit (bit 6) of CALR1 must always be cleared to 0. The
interrupt bit, bit 7 of IRQ3, will report an error in the
calibration process. The error could include the line
becoming off-hook during the common mode balance
calibration.
During all calibrations, the calibration engine controls
VTIP and VRING to provide the correct external voltage
conditions for the calibration algorithm. The TIP and
RING leads must not be connected to ground during
any calibration.
The leakage calibrations (CALR1, bits 4–5) can be done
at regular intervals to provide optimal performance over
temperature
variations.
The
TIP/RING
leakage
calibrations can be performed every hour. Invoke these
leakage calibrations, only during on-hook, by setting
CALR1 to 0xB0. The leakage calibration takes 5 ms and
interferes with dc feed and voice transmission during its
process.
4.4.1. Common Mode Calibration
To optimize common mode (longitudinal) balance
performance, it is recommended that the user perform
the following steps when running the common-mode
calibration routine:
1. Write the Register values as shown in Table 15.
These coefficient values select a 600
impedance
synthesis
2. Set Common Mode Balance Interrupt
(IRQEN3 = 0x80)
3. Set CALR2 = 0x01. This enables only the AC
longitudinal balance calibration routine (CALCMBAL)
4. Set CALR2 = 0x80. This begins the calibration
process.
5. Wait for the CALR1 register to clear to 0x0,
indicating the longitudinal balance calibration is
complete (up to 100ms).
6. Ensure that a common mode balance error interrupt
did not occur. Retry calibration if true.
7. Rewrite desired register values that were changed
during this calibration.
During all calibrations, the calibration engine controls
VTIP and VRING to provide the correct external voltage
conditions for the calibration algorithm. The TIP and
RING leads must not be connected to ground during
any calibration. Note that the channel being calibrated
must be on-hook.
Table 14. Register and RAM Locations used for Loop Monitoring
Parameter
Register/RAM
Mnemonic
Register/
RAM Bits
Measurement Range
LSB Size
Effective
Resolution
Loop Voltage Sense
(VTIP – VRING)
VLOOP
VLOOP[15:0]
0 to 64.07 V
64.07 to 160.173 V
4.907 mV
251 mV
628 mV
TIP Voltage Sense
VTIP
VTIP[15:0]
0 to 64.07 V
64.07 V to 160.173 V
4.907 mV
251 mV
628 mV
RING Voltage Sense
VRING
VRING[15:0]
0 to 64.07 V
64.07 V to 160.173 mA
4.907 mV
251 mV
628 mV
Loop Current Sense
ILOOP
ILOOP[15:0]
0 to 101.09 mA
3.907
A500 A*
Longitudinal Current
Sense
ILONG
ILONG[15:0]
0 to 101.09 mA
3.907
A500 A*
Battery Voltage Sense
VBAT
VBAT[15:0]
0 to 64.07 V
64.07 to 160.173 V
4.907 mV
251 mV
628 mV
*Note: ILOOP and ILONG are calculated values based on measured IQ1–IQ4 currents. The resulting effective resolution is
approximately 500
A.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPZ2D391MHD | CAP ALUM 390UF 200V 20% RADIAL |
| SI3230PPQX-EVB | BOARD EVAL W/DISCRETE INTERFACE |
| M3UFK-1636R | IDC CABLE - MKS16K/MC16M/MCF16K |
| A3RRB-1018G | IDC CABLE - APR10B/AE10G/APR10B |
| SI3225PPTX-EVB | BOARD EVAL W/DISCRETE INTERFACE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI3232DCX-EVB | 功能描述:子卡和OEM板 Si3232 DAUGHTER CARD RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| SI3232-FQ | 功能描述:電信線路管理 IC DUAL CH SLIC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| SI3232-FQR | 制造商:Silicon Laboratories Inc 功能描述: |
| SI3232-G-FQ | 功能描述:電信線路管理 IC Dual-Channel SLIC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| SI3232-G-FQR | 功能描述:電信線路管理 IC Dual-CH SLIC only Internal 65 Vrms RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。