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參數(shù)資料
| 型號： | SI3232DC0-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 75/128頁 |
| 文件大?。?/td> | 0K |
| 描述： | DAUGHTER CARD W/SI3200 INTERFACE |
| 標準包裝： | 1 |
| 系列： | ProSLIC® |
| 主要目的： | 接口，模擬前端（AFE） |
| 已用 IC / 零件： | Si3232 |
| 已供物品： | 板，CD |
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Si3232
50
Preliminary Rev. 0.96
Not
Recommended
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When a resource reaches an interrupt condition, it
signals an interrupt to the interrupt control block. The
interrupt control block then sets the associated bit in the
interrupt status register if the mask bit for that interrupt
is set. The INT pin is a NOR of the bits of the interrupt
status registers. Therefore, if a bit in the interrupt status
registers is asserted, IRQ asserts low. Upon receiving
the interrupt, the interrupt handler should read interrupt
status
registers
to
determine
which
resource
is
requesting service. All interrupt bits in the interrupt
status registers, IRQ0–IRQ3, are cleared following a
register read operation. While the interrupt status
registers are non-zero, the INT pin remains asserted.
4.16. SPI Control Interface
The Si3232 has a 4-wire serial peripheral interface
(SPI) control bus modeled after commonly-available
micro-controller and serial peripheral devices. The
interface consists of a clock (SCLK), chip select (CSB),
serial data input (SDI), and serial data output (SDO). In
addition, the Si3232 includes a serial data through
output (SDI_THRU) to support daisy chain operation of
up to eight devices (up to sixteen channels). The device
can operate with both 8-bit and 16-bit SPI controllers.
Each SPI operation consists of a control byte, an
address byte (of which only the seven LSBs are used
internally), and either one or two data bytes depending
on the width of the controller and whether the access is
to a direct or indirect register. Bytes are always
transmitted MSB first.
There are a number of variations of usage on this four-
wire interface as follows:
Continuous clocking. During continuous clocking,
the data transfers are controlled by the assertion of
the CSB pin. CSB must be asserted before the
falling edge of SCLK on which the first bit of data is
expected during a read cycle and must remain low
for the duration of the 8-bit transfer (command/
address or data), going high after the last rising of
SCLK after the transfer.
Clock only during transfer. In this mode, the clock
cycles only during the actual byte transfers. Each
byte transfer will consist of eight clock cycles in a
return to 1 format.
SDI/SDO wired operation. Independent of the
clocking options described, SDI and SDO can be
treated as two separate lines or wired together if the
master is capable of tri-stating its output during the
data byte transfer of a read operation.
Soft reset. The SPI state machine resets whenever
CSB is asserted during an operation on an SCLK
cycle that is not a multiple of eight. This provides a
mechanism for the controller to force the state
machine to a known state in the case where the
controller and the device appear to be out of
synchronization.
The control byte has the following structure and is
presented on the SDI pin MSB first. The bits are defined
in Table 31.
7
65
432
10
BRDCST
R/W
REG/RAM Reserved
CID[0]
CID[1]
CID[2]
CID[3]
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